Visible to Intel only — GUID: sam1412665041553
Ixiasoft
Visible to Intel only — GUID: sam1412665041553
Ixiasoft
1.1.1. Resource Utilization and Performance
The Intel® Quartus® Prime software configures the PLL according to the settings you apply in the ALTLVDS_RX and ALTLVDS_TX parameter editor. All supported devices provide the option to use an external PLL, which requires you to enter the appropriate PLL parameters.
When the ALTLVDS_TX and ALTLVDS_RX IP cores are instantiated without the external PLL option, they use one PLL per instance. During compilation, if directed to do so, the compiler tries to merge PLLs whenever possible to minimize resource usage.
The Arria, Cyclone® , Hardcopy, and Stratix series support the Use Shared PLL(s) for Receiver and Transmitter option to allow both the ALTLVDS_TX and ALTLVDS_RX IP cores to share a PLL. The Intel® Quartus® Prime software lets the transmitter and receiver share the same PLL when both use identical input clock sources, identical pll_areset sources, identical deserialization factors, and identical output settings. For example, the Intel® Quartus® Prime software displays the following message when the PLL merges successfully:
Info: Receiver fast PLL <lvds_rx PLL name>
and transmitter fast PLL <lvds_tx PLL name> are merged
together
The Intel® Quartus® Prime software displays the following message when it cannot merge the PLLs for the LVDS transmitter and receiver pair in the design:
Warning: Can't merge transmitter-only fast PLL
<lvds_tx PLL name> and receiver-only fast PLL <lvds_rx PLL
name>
For the Stratix series, the side I/O banks contain dedicated SERDES circuitry, which includes the PLLs, serial shift registers, and parallel registers. The transmit and receive functions use varying numbers of LEs depending on the number of channels, serialization, and deserialization factors. For best performance, manually place these LEs in columns as close as possible to the SERDES circuitry and LVDS pins. By default, the Intel® Quartus® Prime software places these LEs automatically during placement and routing.
The Cyclone® series uses DDIO registers as part of the SERDES interface. Because data is clocked on both the rising edge and falling edge, the clock frequency must be half the data rate; therefore, the PLL runs at half the frequency of the data rate. The core clock frequency for the transmitter is data rate divided by serialization factor (J). For the odd serialization factors, depending on the output clock-divide factor (B) and device family, an optional core clock frequency of data rate divided by two times the serialization factor (J) is also available.
Use the following tables to determine the clock and data rate relationships.
Clock Type | J = Even | J = Odd |
---|---|---|
Fast Clock | Data Rate / 2 | Data Rate / 2 |
Slow Clock (outclock) | Data Rate / 2 * B | Data Rate / 2 * B |
Core Clock | Data Rate / J | Data Rate / J |
Clock Type | J = Even | J = Odd |
---|---|---|
Fast Clock | Data Rate / 2 | Data Rate / 2 |
Slow Clock (outclock) | Data Rate / J | Data Rate / J |