Clock Manager Module Address Map

Registers in the Clock Manager module

Base Address: 0xFFD04000

Clock Manager Module

Register Offset Width Access Reset Value Description
ctrl 0x0 32 RW 0x5 Control Register
bypass 0x4 32 RW 0xB PLL Bypass Register
inter 0x8 32 RW 0x0 Interrupt Status Register
intren 0xC 32 RW 0x0 Interrupt Enable Register
dbctrl 0x10 32 RW 0x3 Debug clock Control Register
stat 0x14 32 RO 0x0 Status Register

Main PLL Group

Register Offset Width Access Reset Value Description
vco 0x40 32 RW 0x8001000D Main PLL VCO Control Register
misc 0x44 32 RW 0x4002 Main PLL VCO Advanced Control Register
mpuclk 0x48 32 RW 0x0 Main PLL C0 Control Register for Clock mpu_clk
mainclk 0x4C 32 RW 0x0 Main PLL C1 Control Register for Clock main_clk
dbgatclk 0x50 32 RW 0x0 Main PLL C2 Control Register for Clock dbg_base_clk
mainqspiclk 0x54 32 RW 0x3 Main PLL C3 Control Register for Clock main_qspi_clk
mainnandsdmmcclk 0x58 32 RW 0x3 Main PLL C4 Control Register for Clock main_nand_sdmmc_clk
cfgs2fuser0clk 0x5C 32 RW 0xF Main PLL C5 Control Register for Clock cfg_s2f_user0_clk
en 0x60 32 RW 0x3FF Enable Register
maindiv 0x64 32 RW 0x0 Main Divide Register
dbgdiv 0x68 32 RW 0x4 Debug Divide Register
tracediv 0x6C 32 RW 0x0 Debug Trace Divide Register
l4src 0x70 32 RW 0x0 L4 MP SP APB Clock Source
stat 0x74 32 RO 0x0 Main PLL Output Counter Reset Ack Status Register

Peripheral PLL Group

Register Offset Width Access Reset Value Description
vco 0x80 32 RW 0x8001000D Peripheral PLL VCO Control Register
misc 0x84 32 RW 0x4002 Peripheral PLL VCO Advanced Control Register
emac0clk 0x88 32 RW 0x1 Peripheral PLL C0 Control Register for Clock emac0_clk
emac1clk 0x8C 32 RW 0x1 Peripheral PLL C1 Control Register for Clock emac1_clk
perqspiclk 0x90 32 RW 0x1 Peripheral PLL C2 Control Register for Clock periph_qspi_clk
pernandsdmmcclk 0x94 32 RW 0x1 Peripheral PLL C3 Control Register for Clock periph_nand_sdmmc_clk
perbaseclk 0x98 32 RW 0x1 Peripheral PLL C4 Control Register for Clock periph_base_clk
s2fuser1clk 0x9C 32 RW 0x1 Peripheral PLL C5 Control Register for Clock s2f_user1_clk
en 0xA0 32 RW 0xFFF Enable Register
div 0xA4 32 RW 0x0 Divide Register
gpiodiv 0xA8 32 RW 0x1 GPIO Divide Register
src 0xAC 32 RW 0x15 Flash Clock Source Register
stat 0xB0 32 RO 0x0 Peripheral PLL Output Counter Reset Ack Status Register

SDRAM PLL Group

Register Offset Width Access Reset Value Description
vco 0xC0 32 RW 0x8001000D SDRAM PLL VCO Control Register
ctrl 0xC4 32 RW 0x4002 SDRAM PLL VCO Advanced Control Register
ddrdqsclk 0xC8 32 RW 0x1 SDRAM PLL C0 Control Register for Clock ddr_dqs_clk
ddr2xdqsclk 0xCC 32 RW 0x1 SDRAM PLL C1 Control Register for Clock ddr_2x_dqs_clk
ddrdqclk 0xD0 32 RW 0x1 SDRAM PLL C2 Control Register for Clock ddr_dq_clk
s2fuser2clk 0xD4 32 RW 0x1 SDRAM PLL C5 Control Register for Clock s2f_user2_clk
en 0xD8 32 RW 0xF Enable Register
stat 0xDC 32 RO 0x0 SDRAM PLL Output Counter Reset Ack Status Register

Altera Group

Register Offset Width Access Reset Value Description
alt_mpuclk 0xE0 32 RW 0x1 Altera Group Main PLL C0 Control Register for Clock mpu_clk
alt_mainclk 0xE4 32 RW 0x3 Altera Group Main PLL C1 Control Register for Clock main_clk
alt_dbgatclk 0xE8 32 RW 0x3 Altera Group Main PLL C2 Control Register for Clock dbg_base_clk