vco

Contains settings that control the SDRAM PLL VCO. The VCO output frequency is the input frequency multiplied by the numerator (M+1) and divided by the denominator (N+1). Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD040C0`

Offset: 0xC0

Access: RW

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`regextsel` `RW 0x1`	`outreset` `RW 0x0`						`outresetall` `RW 0x0`	`ssrc` `RW 0x0`		`denom` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`numer` `RW 0x1`													`pwrdn` `RW 0x1`	`en` `RW 0x0`	`bgpwrdn` `RW 0x1`

vco Fields

Bit

Name

Description

Access

Reset

regextsel

If set to '1', the external regulator is selected for the PLL. If set to '0', the internal regulator is slected. It is strongly recommended to select the external regulator while the PLL is not enabled (in reset), and then disable the external regulater once the PLL becomes enabled. Software should simulateously update the 'Enable' bit and the 'External Regulator Input Select' in the same write access to the VCO register. When the 'Enable' bit is clear, the 'External Regulator Input Select' should be set, and vice versa. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit.

RW

0x1

30:25

outreset

Resets the individual PLL output counter. For software to change the PLL output counter without producing glitches on the respective clock, SW must set the VCO register respective Output Counter Reset bit. Software then polls the respective Output Counter Reset Acknowledge bit in the Output Counter Reset Ack Status Register. Software then writes the appropriate counter register, and then clears the respective VCO register Output Counter Reset bit. LSB 'outreset[0]' corresponds to PLL output clock C0, etc. If set to '1', reset output divider, no clock output from counter. If set to '0', counter is not reset. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit.

RW

0x0

outresetall

Before releasing Bypass, All Output Counter Reset must be set and cleared by software for correct clock operation. If '1', Reset phase multiplexer and output counter state. So that after the assertion all the clocks output are start from rising edge align. If '0', phase multiplexer and output counter state not reset and no change to the phase of the clock outputs.

RW

0x0

23:22

ssrc

Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk before changing this field. and user documentation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk.

Value	Description
0x0	eosc1_clk
0x1	eosc2_clk
0x2	f2s_sdram_ref_clk

RW

0x0

21:16

denom

Denominator in VCO output frequency equation. For incremental frequency change, if the new value lead to less than 20% of the frequency change, this value can be changed without resetting the PLL. The Numerator and Denominator can not be changed at the same time for incremental frequency changed.

RW

0x1

15:3

numer

Numerator in VCO output frequency equation. For incremental frequency change, if the new value lead to less than 20% of the frequency change, this value can be changed without resetting the PLL. The Numerator and Denominator can not be changed at the same time for incremental frequency changed.

RW

0x1

pwrdn

If '1', power down analog circuitry. If '0', analog circuitry not powered down.

RW

0x1

en

If '1', VCO is enabled. If '0', VCO is in reset.

RW

0x0

bgpwrdn

If '1', powers down bandgap. If '0', bandgap is not power down.

RW

0x1