Altera Group Register Descriptions Contains registers with settings. Offset: 0xe0 alt_mpuclk Contains settings that control clock mpu_clk generated from the C0 output of the Main PLL. Only reset by a cold reset. alt_mainclk Main PLL C1 Control Register for Clock main_clk. Contains settings that control clock main_clk generated from the C1 output of the Main PLL. Only reset by a cold reset. alt_dbgatclk Main PLL C2 Control Register for Clock dbg_at_clk. Contains settings that control clock dbg_base_clk generated from the C2 output of the Main PLL. Only reset by a cold reset.