vco

Contains settings that control the Main PLL VCO. The VCO output frequency is the input frequency multiplied by the numerator (M+1) and divided by the denominator (N+1). The VCO input clock source is always eosc1_clk. Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD04040`

Offset: 0x40

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`regextsel` `RW 0x1`	`outreset` `RW 0x0`						`outresetall` `RW 0x0`	`Reserved`		`denom` `RW 0x1`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`numer` `RW 0x1`													`pwrdn` `RW 0x1`	`en` `RW 0x0`	`bgpwrdn` `RW 0x1`

vco Fields

Bit	Name	Description	Access	Reset
31	`regextsel`	If set to '1', the external regulator is selected for the PLL. If set to '0', the internal regulator is slected. It is strongly recommended to select the external regulator while the PLL is not enabled (in reset), and then disable the external regulater once the PLL becomes enabled. Software should simulateously update the 'Enable' bit and the 'External Regulator Input Select' in the same write access to the VCO register. When the 'Enable' bit is clear, the 'External Regulator Input Select' should be set, and vice versa. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit.	`RW`	`0x1`
30:25	`outreset`	Resets the individual PLL output counter. For software to change the PLL output counter without producing glitches on the respective clock, SW must set the VCO register respective Output Counter Reset bit. Software then polls the respective Output Counter Reset Acknowledge bit in the Output Counter Reset Ack Status Register. Software then writes the appropriate counter register, and then clears the respective VCO register Output Counter Reset bit. LSB 'outreset[0]' corresponds to PLL output clock C0, etc. If set to '1', reset output divider, no clock output from counter. If set to '0', counter is not reset. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit.	`RW`	`0x0`
24	`outresetall`	Before releasing Bypass, All Output Counter Reset must be set and cleared by software for correct clock operation. If '1', Reset phase multiplexer and all output counter state. So that after the assertion all the clocks output are start from rising edge align. If '0', phase multiplexer and output counter state not reset and no change to the phase of the clock outputs.	`RW`	`0x0`
21:16	`denom`	Denominator in VCO output frequency equation. For incremental frequency change, if the new value lead to less than 20% of the frequency change, this value can be changed without resetting the PLL. The Numerator and Denominator can not be changed at the same time for incremental frequency changed.	`RW`	`0x1`
15:3	`numer`	Numerator in VCO output frequency equation. Note that the valid range for this field is 0x000 to 0xFFF (0 to 4095). The most significant bit of this field is reserved and should not be used. For incremental frequency change, if the new value lead to less than 20% of the frequency change, this value can be changed without resetting the PLL. The Numerator and Denominator can not be changed at the same time for incremental frequency changed.	`RW`	`0x1`
2	`pwrdn`	If '1', power down analog circuitry. If '0', analog circuitry not powered down.	`RW`	`0x1`
1	`en`	If '1', VCO is enabled. If '0', VCO is in reset.	`RW`	`0x0`
0	`bgpwrdn`	If '1', powers down bandgap. If '0', bandgap is not power down.	`RW`	`0x1`