div
Contains fields that control clock dividers for clocks derived from the Peripheral PLL
Fields are only reset by a cold reset.
| Module Instance | Base Address | Register Address |
|---|---|---|
| clkmgr | 0xFFD04000 | 0xFFD040A4 |
Offset: 0xA4
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
can1clk RW 0x0 |
can0clk RW 0x0 |
spimclk RW 0x0 |
usbclk RW 0x0 |
|||||||||||
div Fields
| Bit | Name | Description | Access | Reset | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 11:9 | can1clk | The can1_clk is divided down from the periph_base_clk by the value specified in this field.
|
RW | 0x0 | ||||||||||||||||||
| 8:6 | can0clk | The can0_clk is divided down from the periph_base_clk by the value specified in this field.
|
RW | 0x0 | ||||||||||||||||||
| 5:3 | spimclk | The spi_m_clk is divided down from the periph_base_clk by the value specified in this field.
|
RW | 0x0 | ||||||||||||||||||
| 2:0 | usbclk | The usb_mp_clk is divided down from the periph_base_clk by the value specified in this field.
|
RW | 0x0 |