inter

Contains fields that indicate the PLL lock status. Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD04008`

Offset: 0x8

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`sdrplllocked` `RO 0x0`	`perplllocked` `RO 0x0`	`mainplllocked` `RO 0x0`	`sdrplllost` `RW 0x0`	`perplllost` `RW 0x0`	`mainplllost` `RW 0x0`	`sdrpllachieved` `RW 0x0`	`perpllachieved` `RW 0x0`	`mainpllachieved` `RW 0x0`

inter Fields

Bit	Name	Description	Access	Reset
8	`sdrplllocked`	If 1, the SDRAM PLL is currently locked. If 0, the SDRAM PLL is currently not locked.	`RO`	`0x0`
7	`perplllocked`	If 1, the Peripheral PLL is currently locked. If 0, the Peripheral PLL is currently not locked.	`RO`	`0x0`
6	`mainplllocked`	If 1, the Main PLL is currently locked. If 0, the Main PLL is currently not locked.	`RO`	`0x0`
5	`sdrplllost`	If 1, the SDRAM PLL has lost lock at least once since this bit was cleared. If 0, the SDRAM PLL has not lost lock since this bit was cleared.	`RW`	`0x0`
4	`perplllost`	If 1, the Peripheral PLL has lost lock at least once since this bit was cleared. If 0, the Peripheral PLL has not lost lock since this bit was cleared.	`RW`	`0x0`
3	`mainplllost`	If 1, the Main PLL has lost lock at least once since this bit was cleared. If 0, the Main PLL has not lost lock since this bit was cleared.	`RW`	`0x0`
2	`sdrpllachieved`	If 1, the SDRAM PLL has achieved lock at least once since this bit was cleared. If 0, the SDRAM PLL has not achieved lock since this bit was cleared.	`RW`	`0x0`
1	`perpllachieved`	If 1, the Peripheral PLL has achieved lock at least once since this bit was cleared. If 0, the Peripheral PLL has not achieved lock since this bit was cleared.	`RW`	`0x0`
0	`mainpllachieved`	If 1, the Main PLL has achieved lock at least once since this bit was cleared. If 0, the Main PLL has not achieved lock since this bit was cleared.	`RW`	`0x0`