en

Contains fields that control clock enables for clocks derived from the Main PLL. 1: The clock is enabled. 0: The clock is disabled. Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD04060`

Offset: 0x60

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`						`s2fuser0clk` `RW 0x1`	`cfgclk` `RW 0x1`	`dbgtimerclk` `RW 0x1`	`dbgtraceclk` `RW 0x1`	`dbgclk` `RW 0x1`	`dbgatclk` `RW 0x1`	`l4spclk` `RW 0x1`	`l4mpclk` `RW 0x1`	`l3mpclk` `RW 0x1`	`l4mainclk` `RW 0x1`

en Fields

Bit	Name	Description	Access	Reset
9	`s2fuser0clk`	Enables clock s2f_user0_clk output. and user documentation refer to s2f_user0_clk as h2f_user0_clk.	`RW`	`0x1`
8	`cfgclk`	Enables clock cfg_clk output	`RW`	`0x1`
7	`dbgtimerclk`	Enables clock dbg_timer_clk output	`RW`	`0x1`
6	`dbgtraceclk`	Enables clock dbg_trace_clk output	`RW`	`0x1`
5	`dbgclk`	Enables clock dbg_clk output	`RW`	`0x1`
4	`dbgatclk`	Enables clock dbg_at_clk output	`RW`	`0x1`
3	`l4spclk`	Enables clock l4_sp_clk output	`RW`	`0x1`
2	`l4mpclk`	Enables clock l4_mp_clk output	`RW`	`0x1`
1	`l3mpclk`	Enables clock l3_mp_clk output	`RW`	`0x1`
0	`l4mainclk`	Enables clock l4_main_clk output	`RW`	`0x1`