en

Contains fields that control clock enables for clocks derived from the Peripheral PLL 1: The clock is enabled. 0: The clock is disabled. Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD040A0`

Offset: 0xA0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`				`qspiclk` `RW 0x1`	`nandclk` `RW 0x1`	`nandxclk` `RW 0x1`	`sdmmcclk` `RW 0x1`	`s2fuser1clk` `RW 0x1`	`gpioclk` `RW 0x1`	`can1clk` `RW 0x1`	`can0clk` `RW 0x1`	`spimclk` `RW 0x1`	`usbclk` `RW 0x1`	`emac1clk` `RW 0x1`	`emac0clk` `RW 0x1`

en Fields

Bit	Name	Description	Access	Reset
11	`qspiclk`	Enables clock qspi_clk output	`RW`	`0x1`
10	`nandclk`	Enables clock nand_clk output nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and the nand_x_clk Enable should always be asserted before the nand_clk Enable is asserted. A brief delay is also required between switching the enables (8 * nand_clk period).	`RW`	`0x1`
9	`nandxclk`	Enables clock nand_x_clk output nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and the nand_x_clk Enable should always be asserted before the nand_clk Enable is asserted. A brief delay is also required between switching the enables (8 * nand_clk period).	`RW`	`0x1`
8	`sdmmcclk`	Enables clock sdmmc_clk output	`RW`	`0x1`
7	`s2fuser1clk`	Enables clock s2f_user1_clk output. and user documentation refer to s2f_user1_clk as h2f_user1_clk.	`RW`	`0x1`
6	`gpioclk`	Enables clock gpio_clk output	`RW`	`0x1`
5	`can1clk`	Enables clock can1_clk output	`RW`	`0x1`
4	`can0clk`	Enables clock can0_clk output	`RW`	`0x1`
3	`spimclk`	Enables clock spi_m_clk output	`RW`	`0x1`
2	`usbclk`	Enables clock usb_mp_clk output	`RW`	`0x1`
1	`emac1clk`	Enables clock emac1_clk output	`RW`	`0x1`
0	`emac0clk`	Enables clock emac0_clk output	`RW`	`0x1`