gpiodiv
Contains a field that controls the clock divider for the GPIO De-bounce clock.
Only reset by a cold reset.
| Module Instance | Base Address | Register Address |
|---|---|---|
| clkmgr | 0xFFD04000 | 0xFFD040A8 |
Offset: 0xA8
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
gpiodbclk RW 0x1 |
||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
gpiodbclk RW 0x1 |
|||||||||||||||
gpiodiv Fields
| Bit | Name | Description | Access | Reset |
|---|---|---|---|---|
| 23:0 | gpiodbclk | The gpio_db_clk is divided down from the periph_base_clk by the value plus one specified in this field. The value 0 (divide by 1) is illegal. A value of 1 indicates divide by 2, 2 divide by 3, etc. |
RW | 0x1 |