ddrdqclk

Contains settings that control clock ddr_dq_clk generated from the C2 output of the SDRAM PLL. Fields are only reset by a cold reset.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD040D0`

Offset: 0xD0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`											`phase` `RW 0x0`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`phase` `RW 0x0`							`cnt` `RW 0x1`

ddrdqclk Fields

Bit	Name	Description	Access	Reset
20:9	`phase`	Increment the phase of the VCO output by the value in this field multiplied by 45 degrees. The accumulated phase shift is the total shifted amount since the last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco control register. In order to guarantee the phase shift to a known value, 'SDRAM clocks output phase align' bit should be asserted before programming this field. This field is only writeable by SW when it is zero. HW updates this field in real time as the phase adjustment is being made. SW may poll this field waiting for zero indicating the phase adjustment has completed by HW.	`RW`	`0x0`
8:0	`cnt`	Divides the VCO frequency by the value+1 in this field.	`RW`	`0x1`