intren
Module Instance | Base Address | Register Address |
---|---|---|
clkmgr | 0xFFD04000 | 0xFFD0400C |
Offset: 0xC
Access: RW
Bit Fields | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
sdrplllost RW 0x0 |
perplllost RW 0x0 |
mainplllost RW 0x0 |
sdrpllachieved RW 0x0 |
perpllachieved RW 0x0 |
mainpllachieved RW 0x0 |
intren Fields
Bit | Name | Description | Access | Reset |
---|---|---|---|---|
5 | sdrplllost | When set to 1, the SDRAM PLL lost lock bit is ORed into the Clock Manager interrupt output. When set to 0 the SDRAM PLL lost lock bit is not ORed into the Clock Manager interrupt output. |
RW | 0x0 |
4 | perplllost | When set to 1, the Peripheral PLL lost lock bit is ORed into the Clock Manager interrupt output. When set to 0 the Peripheral PLL lost lock bit is not ORed into the Clock Manager interrupt output. |
RW | 0x0 |
3 | mainplllost | When set to 1, the Main PLL lost lock bit is ORed into the Clock Manager interrupt output. When set to 0 the Main PLL lost lock bit is not ORed into the Clock Manager interrupt output. |
RW | 0x0 |
2 | sdrpllachieved | When set to 1, the SDRAM PLL achieved lock bit is ORed into the Clock Manager interrupt output. When set to 0 the SDRAM PLL achieved lock bit is not ORed into the Clock Manager interrupt output. |
RW | 0x0 |
1 | perpllachieved | When set to 1, the Peripheral PLL achieved lock bit is ORed into the Clock Manager interrupt output. When set to 0 the Peripheral PLL achieved lock bit is not ORed into the Clock Manager interrupt output. |
RW | 0x0 |
0 | mainpllachieved | When set to 1, the Main PLL achieved lock bit is ORed into the Clock Manager interrupt output. When set to 0 the Main PLL achieved lock bit is not ORed into the Clock Manager interrupt output. |
RW | 0x0 |