dbctrl

Contains fields that control the debug clocks.

Module Instance	Base Address	Register Address
`clkmgr`	`0xFFD04000`	`0xFFD04010`

Offset: 0x10

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`														`ensfmdwr` `RW 0x1`	`stayosc1` `RW 0x1`

dbctrl Fields

Bit	Name	Description	Access	Reset
1	`ensfmdwr`	When this bit is set the debug clocks will be affected by the assertion of Safe Mode on a warm reset if Stay OSC1 is not set. When this bit is clear the debug clocks will not be affected by the assertion of Safe Mode on a warm reset. If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe Mode bit is cleared independent of this bit. The reset value of this bit is applied on a cold reset; warm reset has no effect on this bit.	`RW`	`0x1`
0	`stayosc1`	When this bit is set the debug root clock (Main PLL C2 output) will always be bypassed to the EOSC1_clk independent of any other clock manager settings. When clear the debug source will be a function of register settings in the clock manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk, and dbg_timer_clk. The reset value for this bit is applied on a cold reset. Warm reset has no effect on this bit.	`RW`	`0x1`