F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example User Guide

ID 815243
Date 4/01/2024
Public

2.6.1. Test Procedure

After you compile the F-Tile Low Latency 100G Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP.

To turn on the System Console and test the hardware design example, follow these steps:

  1. After the hardware design example is configured on the Agilex™ 7 device, in the Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest .
  3. Type source main.tcl to open a connection to the JTAG master.
  4. Run the set_jtag 1 command in the System Console.

You can program the IP with the following design example commands:
  • chkphy_status: Displays the clock frequencies and PHY lock status.
  • chkmac_stats: Displays the values in the MAC statistics counters.
  • clear_all_stats: Clears the IP statistics counters.
  • start_pkt_gen: Starts the packet generator.
  • stop_pkt_gen: Stops the packet generator.
  • loop_on: Turns on internal serial loopback
  • loop_off: Turns off internal serial loopback.
  • reg_read: Returns the IP register value.
  • reg_write: Writes to the IP register at address.

The successful test run displays output confirming the following behavior:

  1. Turning off packet generation
  2. Enabling loopback
  3. Waiting for RX clock to settle
  4. Printing PHY status
  5. Clearing MAC statistics counters
  6. Sending packets
  7. Reading MAC statistics counters
  8. Printing MAC statistics counters, which shows 0 in all error counters.
Figure 8. Sample Test Output
Figure 9. Sample Test Output—RX Statistics Counters
Figure 10. Sample Test Output—TX Statistics Counters