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1.1. Directory Structure
1.2. Generating the Design Example
1.3. Command Line IP Generation Flow
1.4. Generating Tile Files
1.5. Simulating the F-Tile Low Latency 100G Ethernet Intel® FPGA IP Design Example Testbench
1.6. Compiling and Configuring the Design Example in Hardware
1.7. Testing the Design Example in Hardware
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2.6.1. Test Procedure
After you compile the F-Tile Low Latency 100G Ethernet Intel® FPGA IP design example and configure it on your Agilex™ 7 device, you can use the System Console to program the IP.
To turn on the System Console and test the hardware design example, follow these steps:
- After the hardware design example is configured on the Agilex™ 7 device, in the Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
- In the Tcl Console pane, type cd hwtest to change directory to /hardware_test_design/hwtest .
- Type source main.tcl to open a connection to the JTAG master.
- Run the set_jtag 1 command in the System Console.
You can program the IP with the following design example commands:
- chkphy_status: Displays the clock frequencies and PHY lock status.
- chkmac_stats: Displays the values in the MAC statistics counters.
- clear_all_stats: Clears the IP statistics counters.
- start_pkt_gen: Starts the packet generator.
- stop_pkt_gen: Stops the packet generator.
- loop_on: Turns on internal serial loopback
- loop_off: Turns off internal serial loopback.
- reg_read: Returns the IP register value.
- reg_write: Writes to the IP register at address.
The successful test run displays output confirming the following behavior:
- Turning off packet generation
- Enabling loopback
- Waiting for RX clock to settle
- Printing PHY status
- Clearing MAC statistics counters
- Sending packets
- Reading MAC statistics counters
- Printing MAC statistics counters, which shows 0 in all error counters.
Figure 8. Sample Test Output
Figure 9. Sample Test Output—RX Statistics Counters
Figure 10. Sample Test Output—TX Statistics Counters