Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813963
Date 7/08/2024
Public
Document Table of Contents

3.5. VCC Core Board Current Slew Rate

The VCC core fabric has a very high current slew rate but some of that is filtered out by the metal-insulator-metal (MIM) capacitors as they provide the lowest impedance to the load because of their proximity. With addition of OPDs, most of the remaining fast edges are filtered out, leaving the board cavity capacitors and voltage regulator capacitors to handle only a fraction of the die level current.

You must ensure the PDN can deliver the current specified at the package balls. The Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails section describes the recommended PCB system-level simulation to ensure the voltage tolerance or specification at package balls are met through the design.