Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813963
Date 7/08/2024
Public
Document Table of Contents

2.3.1. Power Nets

This section describes the Agilex™ 5 device family power nets and their subsystem details along with their board-level connection based on the recommended power trees described in the Power Tree section.

For more detailed board-level connection specification, refer to the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs.