2.3.2. Power Rails Tolerance
This section describes the power rails tolerance and budget (AC tolerance + VR accuracy) on board at package level for the Agilex™ 5 device family. The rail tolerance must be met at the FPGA package ball. You must consider the following instructions to measure the rail tolerance:
- VCCL (core power net) measurement is taken at the FPGA remote differential sense lines (there are assigned differential sense pins at FPGA package) with the scope set to bandwidth limited at 20 MHz.
- Other power rails (except for VCCL (core power)), the rail tolerance must be met at the board vias on the bottom layer directly connected to the package power balls.
- For all other power rails with the objective to compensate the IR drop on those specific power rails, place their respective voltage regulator sense point within the FPGA pin field, connecting to one of the rail's BGA pins which represents the worst IR drop on the path.
| Power Tree Rail Name | Vnom (Required) (V) |
Recommended VR Accuracy (% of Vnom) |
Recommended VR Ripple (% of Vnom) |
Recommended AC Transient (% of Vnom) |
Maximum AC Tolerance + VR Accuracy1 (% of Vnom) |
|---|---|---|---|---|---|
| VCCL | SmartVID (0.8) | ±0.5% | ±2.5% | ±3% | |
| P0V8_GR1 | 0.8 | ±0.5% | ±2.5% | ±3% | |
| P1V0_GR1 | 1.0 | ±0.5% | ±2.0% | ±2.5% | |
| P1V8_GR2a2 :
|
1.8 | ±0.5% | ±2.0% | ±2.5% | |
| P1V8_GR2a2:
|
1.8 | ±0.5% | ±1%3 | ±1.5% | ±3% |
| P1V8_GR2a2:
|
1.8 | ±0.5% | ±1%3 | ±3.5% | ±5% |
| P1V2_GR2b4 :
|
1.2 | ±0.5% | ±1%3 | ±1.5% | ±3% |
| P1V2_GR2b4:
|
1.2 | ±0.5% | ±1%3 | ±3.5% | ±5% |
| VCCIO_HVIO | 3.3/2.5/1.8 | ±0.5% | ±1%3 | ±1.5% | ±3% |
| Power Tree Rail Name | Vnom (Required) (V) |
Recommended VR Accuracy (% of Vnom) |
Recommended VR Ripple (% of Vnom) |
Recommended AC Transient (% of Vnom) |
Maximum AC Tolerance + VR Accuracy1 (% of Vnom) |
|---|---|---|---|---|---|
| VCCL | 0.8 (-4S) 0.78 (-5S) 0.75 (-6S, -6X) |
±0.5% | ±2.5% | ±3% | |
| P1V0_GR1 | 1.0 | ±0.5% | ±2.0% | ±2.5% | |
| P1V8_GR2a2:
|
1.8 | ±0.5% | ±2.0% | ±2.5% | |
| P1V8_GR2a2:
|
1.8 | ±0.5% | ±1%3 | ±1.5% | ±3% |
| P1V8_GR2a2:
|
1.8 | ±0.5% | ±1%3 | ±3.5% | ±5% |
| P1V2_GR2b4:
|
1.2 | ±0.5% | ±1%3 | ±1.5% | ±3% |
| P1V2_GR2b4:
|
1.2 | ±0.5% | ±1%3 | ±3.5% | ±5% |
| VCCIO_HVIO | 3.3/2.5/1.8 | ±0.5% | ±1%3 | ±1.5% | ±3% |
The actual specification for each power rail at package level is listed in the Agilex™ 5 FPGAs and SoCs Device Data Sheet. To reduce the PCB cost, some power rails are merged by using only a single voltage regulator to feed the power rails. The AC + DC specification in this design guideline is based on this design. However, you have the option to not combine the power rails on the PCB in your design.
You can combine the analog power rails on the PCB (provided that the nominal voltages are the same) by using a single voltage regulator on the PCB to feed the power rails to achieve the minimum cost. If you implement this design, you must ensure the power rail specifications of the combined power rails on the PCB and voltage regulator must follow the most stringent specification of those package power rails.
The Agilex™ 5 SmartVID Device PCB Power Rail Tolerance and Agilex™ 5 Fixed Voltage Device PCB Power Rail Tolerance tables show the power rail tolerance (AC tolerance + VR accuracy) based on the power tree in the Power Tree section.
If a different power tree is used, the rail tolerance of each power net must still fall into their recommended grouping category in the Agilex™ 5 SmartVID Device PCB Power Rail Tolerance and Agilex™ 5 Fixed Voltage Device PCB Power Rail Tolerance tables.
1 The specification stands for VR accuracy + (VR ripple + AC transient) rail tolerance and must be measured and met at package pin/ball.
2 Use the tight tolerance requirement in board design for P1V8_GR2a rail.
3 If you select a VR with lower than 1% VR ripple specification, the extra margin is added to recommended AC transient specification.
4 Use the tight tolerance requirement in board design for P1V2_GR2b rail.