Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813963
Date 7/08/2024
Public
Document Table of Contents

1. Agilex™ 5 Power Distribution Network Design Guidelines Overview

This application note provides information for the Agilex™ 5 device family power distribution network (PDN) design guidelines. A solid design guidelines for the Agilex™ 5 device family PDN including fixed decoupling capacitors on board and minimum simulation is proposed.

In the previous FPGA families (for example, the Stratix® 10 and Arria® 10 devices), the PDN tool was used along with power consumption data from the Early Power Estimator (EPE) and the pin connection guidelines to design and optimize board-level PDN. However, due to achieving non-feasible PDN design tool (decoupling capacitors) specifically for core, and with pessimistic results, the PDN tool is not used or supported for the Agilex™ 5 device family.

The information in this application note is intended to provide guidelines to allow you to successfully complete your PDN design, without requiring additional support.

Refer to the Power Management User Guide: Agilex™ 5 FPGAs and SoCs for more information.