2.3.3. Power Nets and Transient Specifications
Rail transient values provided in the following table are used to design and simulate the board level transient power. Choose the recommended load slew rates and step load at FPGA package ball below for PCB-level PDN system simulations and design. The table shows the maximum tolerable step load at FPGA package pin. The recommended step load is connected to FPGA package ball along with the PCB post-layout model (with decoupling capacitors and voltage regulator model excluding package and silicon/die model) in an EDA tool for time domain simulation to meet rail tolerance of respective power net in the Power Rails Tolerance section at the FPGA package ball.
The table shows for the recommended step load at the package ball and step load’s slew rate.
Note: The step load suggested in the table is for a normal application and worst case operation in FPGA and tiles. The step load can also be scaled down if the dynamic current of the target power rail in PTC is smaller than the step load shown in the table.
| Package Power Rails | At Package Balls (Step Load) | DI/dt at Package Balls (for Board Design)-Slew Rate | Notes |
|---|---|---|---|
| DI (A)-Step Load | DI/dt (A/µs)-Slew Rate | ||
| VCC&VCCP A5E007B B15A/B23B/B18A |
0.8 | 26 | The step load is the worst case step load in the design based on 80% utilization of LAB and clock network. |
| VCC&VCCP A5E013B B23A/B32A/M16A/B23B/B18A |
1.5 | 50 | The step load is the worst case step load in the design based on 80% utilization of LAB and clock network. |
| VCC&VCCP A5E028B B23A/B32A/M16A/B23B |
2.5 | 100 | The step load is the worst case step load in the design based on 80% utilization of LAB and clock network. |
| VCC&VCCP A5E065B B23A/B32A |
3.5 | 70 | The step load is the worst case step load in the design based on 80% utilization of LAB and clock network. |
| VCC&VCCP A5E065A B23A/B32A |
3.7 | 74 | The step load is the worst case step load in the design based on 80% utilization of LAB and clock network. |
| VCC&VCCP A5D031 B23D/B32B |
2 | 100 | The step load is the worst case step load in the design based on 80% utilization of LAB and clock network. |
| VCC&VCCP A5D064 B32B |
4.9 | 196 | The step load is the worst case step load in the design based on 80% utilization of LAB and clock network. |
| VCCPT | 0.05 | 7.14 | — |
| VCCRCORE | 0.2 | 5 | — |
| VCCIO_PIO | 0.645 | 10.8 | Current specification is per I/O bank. Each I/O bank consists of 96 x I/Os. More I/O banks can join the same voltage regulator, but current specification stays per I/O bank. |
| VCCL_HPS | 0.016 | 0.15 | — |
| VCCL_HPS_CORE0_CORE1 | 0.01 | 0.1 | — |
| VCCL_HPS_CORE2 | 0.02 | 0.2 | — |
| VCCL_HPS_CORE3 | 0.014 | 0.14 | — |
| VCC_HSSI | 0.053 | 1.66 | For X4 GTS transceiver banks |
| VCCERT_GTS | 0.02 | 2 | For single GTS transceiver channel |
| 0.1 | 0.3 | For X4 GTS transceiver channels | |
| VCCEHT_GTS | 0.01 | 0.37 | For single GTS transceiver channel |
| 0.07 | 0.23 | For X4 GTS transceiver channels |
You must also notice the following:
- Step current at package pin is only provided for critical power rails due to either having high current/power profile at die or being highly sensitive. Agilex™ recommends you to do transient/time domain PDN simulation by using this step load for these critical power rails in the Agilex™ 5 Device Family Transient and Step Load Specifications at Package Pin table to ensure you can meet the voltage specification at package pin. If the voltage specification is not met at package pin, decoupling capacitors must be adjusted.
- Altera does not provide step current for other power rails not mentioned in the Agilex™ 5 Device Family Transient and Step Load Specifications at Package Pin table. Those power rails are called non-critical power rails due to having less sensitivity or low current profile/power consumption on silicon. Altera does not recommend time domain PDN analysis for non-critical power rails. Non-critical power rails PDN design suggested in this application note is guaranteed.
- Altera recommends that you perform DC IR drop analysis for all power rails.