Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813963
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 Power Distribution Network Design Guidelines Overview 2. Power Delivery Overview 3. Board Power Delivery Network Recommendations 4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails 5. PCB PDN Design Guideline for Unused GTS Transceiver 6. PCB Voltage Regulator Recommendation for PCB Power Rails 7. Board Power Delivery Network Simulations 8. Agilex™ 5 Device Family PDN Design Summary 9. Document Revision History for the Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 Power Distribution Network Design Guidelines Overview x
1.1. Device Guidelines Status for Agilex™ 5 Devices
2. Power Delivery Overview x
2.1. Power Architecture 2.2. Rail Merger Requirements 2.3. Power Rails Specification 2.4. Decoupling Capacitors Recommendation
2.1. Power Architecture x
2.1.1. Power Budget 2.1.2. Power Tree
2.1.2. Power Tree x
2.1.2.1. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with SmartVID and GTS Transceiver in the Device Packages 2.1.2.2. Recommended Power Tree for the Agilex™ 5 E-Series and D-Series Devices with Non-SmartVID and GTS Transceiver in the Device Packages
2.3. Power Rails Specification x
2.3.1. Power Nets 2.3.2. Power Rails Tolerance 2.3.3. Power Nets and Transient Specifications
2.3.1. Power Nets x
2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
2.4. Decoupling Capacitors Recommendation x
2.4.1. Agilex™ 5 FPGA Packages Board-Level Decoupling Capacitors Summary 2.4.2. Agilex™ 5 GTS Transceiver Board-Level Decoupling Capacitors Summary
3. Board Power Delivery Network Recommendations x
3.1. Board Decoupling Capacitors Guide 3.2. FPGA Core Fabric VCC Voltage Regulator Selection 3.3. Remote Sense Connections 3.4. Load Line Requirements 3.5. VCC Core Board Current Slew Rate
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails x
4.1. GTS Transceiver Rail Board Connection and LC Filter Recommendation under Noisy Voltage Regulator
5. PCB PDN Design Guideline for Unused GTS Transceiver x
5.1. PDN Design Guideline for Unused GTS Transceiver
1. Agilex™ 5 Power Distribution Network Design Guidelines Overview
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused GTS Transceiver
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 5 Device Family PDN Design Summary
9. Document Revision History for the Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs

8. Agilex™ 5 Device Family PDN Design Summary

The summary of the Agilex™ 5 device family PDN design guidelines is as follow:

  1. Current PDN design guidelines stand for the maximum power consumption—the worst use case.
    • If for any reason (various applications, configurations, or the PTC) power data is lower than the maximum power used for the PDN design guideline, you must scale the recommended decoupling capacitors based on the ratio of design current to the maximum current. Use of ratio is an estimate and time domain simulation are mandatory to ensure meeting package ball voltage specification.
  2. Apply the recommended power-up or power-down sequence grouping on the PCB. For more information, refer to AN 692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, Stratix® 10, and Agilex™ 7 and Pin Management User Guide: Agilex™ 5 FPGAs and SoCs .
  3. Use the recommended power tree presented in the Power Tree section for each Agilex™ 5 device with the suggested merged power nets.
  4. Use the recommended voltage regulators in the power tree or design your own voltage regulator based on the required maximum ripple or total current support per power rail on the PCB-VRM inductors or bulk capacitors must be designed separately. Tables in the Decoupling Capacitors Recommendation section show the FPGA decoupling capacitors and do not include the voltage regulator bulk capacitors.
  5. Use the recommended bottom-side or FPGA periphery decoupling capacitors for each power net.
  6. Use the recommended LC filters for power nets.
  7. Use of sense line for IR drop compensation.
  8. Configure the FPGA to follow the maximum recommended step load allowed at the package pin.
  9. Do post-layout simulation for the IR drop analysis to see if this is within the DC specification at the package pin in the Power Rails Tolerance section.
  10. Do post-layout time domain PCB simulation up to the package pin for critical power nets such as the VCC+VCCP to meet the AC voltage tolerance or specification at the package pin in the Power Rails Tolerance section.
  11. If not meeting the voltage tolerance (DC or AC) at the FPGA package pin, you must check the PCB and update the decoupling capacitors and redo the simulations.
Related Information
Level Two Title