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1. Power Distribution Network Design Guidelines
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused GTS Transceiver
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 5 Device Family PDN Design Summary
9. Document Revision History for the Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs
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8. Agilex™ 5 Device Family PDN Design Summary
The summary of the Agilex™ 5 device family PDN design guidelines is as follow:
- Current PDN design guidelines stand for the maximum power consumption—the worst use case.
- If for any reason (various applications, configurations, or the PTC) power data is lower than the maximum power used for the PDN design guideline, you must scale the recommended decoupling capacitors based on the ratio of design current to the maximum current. Use of ratio is an estimate and time domain simulation is mandatory to ensure meeting package ball voltage specification.
- Apply the required power-up or power-down sequence grouping on the PCB. For more information, refer to AN692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, Stratix® 10, and Agilex™ 7 and Pin Management User Guide: Agilex™ 5 FPGAs and SoCs..
- Use the recommended power tree presented in the Power Tree section for each Agilex™ 5 device with the suggested merged power nets.
- Use the recommended voltage regulators in the power tree or design your own voltage regulator based on the required maximum ripple or total current supporting per power rail on the PCB (VRM inductors or bulk capacitors must be designed separately). Tables in the Decoupling Capacitors Recommendation section show the FPGA decoupling capacitors and do not include the voltage regulator bulk capacitors.
- Use the recommended bottom-side or FPGA periphery decoupling capacitors for each power net.
- Use the recommended LC filters for power nets.
- Use of sense line for IR drop compensation.
- Ensure your FPGA design follows the maximum recommended step load allowed at the package pin.
- Do post-layout simulation for the IR drop analysis to see if this is within the DC specification at the package pin in the Power Rails Tolerance section.
- Recommend to do post-layout time domain PCB simulation up to the package pin for critical power nets such as the VCC+VCCP to meet the AC voltage tolerance or specification at the package pin in the Power Rails Tolerance section.
- If not meeting the voltage tolerance (DC or AC) at the FPGA package pin, you must check the PCB and update the decoupling capacitors and redo the simulations.