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1. Power Distribution Network Design Guidelines
2. Power Delivery Overview
3. Board Power Delivery Network Recommendations
4. Board LC Recommended Filters for Noise Reduction in Combined Power Delivery Rails
5. PCB PDN Design Guideline for Unused GTS Transceiver
6. PCB Voltage Regulator Recommendation for PCB Power Rails
7. Board Power Delivery Network Simulations
8. Agilex™ 5 Device Family PDN Design Summary
9. Document Revision History for the Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs
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3.3. Remote Sense Connections
Die sense pins are provided for the core fabric voltage regulator. The voltage regulator sense line for VCC core must be connected to the differential pair sense lines or pins provided on the package. The voltage regulator feedback inputs shall be connected to this FPGA die remote sense lines.
You are required to use sense lines for Agilex™ 5 core, including the VID and multi-voltage designs.
Note: For those power rails which do not have dedicated sense pins at package level, the IR drop can still be compensated by using a voltage regulator with the sense feedback pin. To find the sense pins, you must do the IR drop analysis along with plotting power or current distribution of that specific power rail at package level to find the pins which are located further from the voltage regulator and have the maximum IR drop.
Note: Any sense line used on the board for that specific power rail must be placed before LC filter. If a sense line is placed after LC filter, it can result in oscillation to the rails and an unstable voltage that is an input to the voltage regulator feedback pin function. If the power rail is using LDO, LC filter is not required.