2.3.1.1. Agilex™ 5 Package Power Nets and Subsystems Details
Device | Power Thermal Calculator (PTC) Rail Name | Board Connections | System Connections |
---|---|---|---|
FPGA | VCC | VCCL, SmartVID, 0.8 V | VCC supplies power to the Core. |
FPGA/PIO | VCCP | VCCP supplies power to the Periphery. | |
FPGA/HPS | VCCL_HPS | VCCL_HPS suppliers’ power to the HPS DSU and periphery circuitry. | |
FPGA/HPS | VCCPLLDIG1_HPS | VCCPLLDIG1_HPS: Digital power supply of the main HPS PLLs. | |
VCCPLLDIG2_HPS | VCCPLLDIG2_HPS: Digital power supply of the peripheral HPS PLLs. | ||
FPGA/HPS | VCCL_HPS_CORE0_CORE1 | Supply power to HPS A55 Core0 and Core1. | |
FPGA/HPS | VCCL_HPS_CORE2 | Supply power to HPS A76 Core2. | |
FPGA/HPS | VCCL_HPS_CORE3 | Supply power to HPS A76 Core3. | |
FPGA/SDM | VCC_IO_SDM | SDM block I/O digital supply voltage sense. | |
FPGA/SDM | VCCL_ADC_SDM | HPS DSU and periphery voltage sense. | |
FPGA/SDM | VCCL_SDM | P0V8_GR1 | SDM power supply. |
FPGA/SDM | VCCPLLDIG_SDM | SDM block PLL power pins. | |
FPGA/SDM | VCCH_SDM | P1V0_GR1 | Voltage rail sense. It is 0.8 V and can be combined with VCCL_SDM for the devices without GTS transceiver. |
FPGA | VCCPT | P1V8_GR2a | Power supply for the IOPLL, programmable power technology, and I/O pre-drivers. |
FPGA/HVIO | VCCPT_HVIO | Pre-driver analog power supply pin for HVIO. | |
FPGA/SDM | VCCIO_SDM | Configuration pins power supply. | |
FPGA/HPS | VCCIO_HPS | The HPS dedicated I/Os support 1.8 V voltage level. | |
FPGA/SDM | VCCFUSEWR_SDM | The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Agilex™ Security architecture. | |
FPGA/HPS | VCCPLL1_HPS | VCCPLL1_HPS: Supply analog power to the main HPS PLLs. | |
VCCPLL2_HPS | VCCPLL2_HPS: Supply analog power to the peripheral HPS PLLs. | ||
FPGA/SDM | VCCADC | ADC power pin for the voltage sensors. | |
FPGA/SDM | VCCPLL_SDM | VCCPLL_SDM supplies analog power to the SDM block PLLs. | |
FPGA/PIO | VCCIO_PIO_T/B | P1V2_GR2b | Power supply voltage pins for the I/O banks. |
FPGA/SDM | VCCIO_PIO_SDM | VCCIO_PIO voltage rail sense line. | |
FPGA | VCCRCORE | Transceiver core power supply. | |
FPGA/HVIO | VCCIO_HVIO | P3V3/2V5/1V8_GR2b | Buffer analog power supply pin for HVIO. |
FPGA/SDM | VCCBAT | VCCBAT | Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register. |
System | Power Thermal Calculator (PTC) Rail Name | Board Connections | System Connections |
---|---|---|---|
FPGA | VCC | VCCL 0.8 V/0.78 V/0.75 V | VCC supplies power to the Core. |
FPGA/PIO | VCCP | VCCP supplies power to the Periphery. | |
FPGA/HPS | VCCL_HPS | VCCL_HPS suppliers’ power to the HPS DSU and periphery circuitry. | |
FPGA/HPS | VCCPLLDIG1_HPS | VCCPLLDIG1_HPS: Digital power supply of the main HPS PLLs. | |
VCCPLLDIG2_HPS | VCCPLLDIG2_HPS: Digital power supply of the peripheral HPS PLLs. | ||
FPGA/HPS | VCCL_HPS_CORE0_CORE1 | Supply power to HPS A55 Core0 and Core1. | |
FPGA/HPS | VCCL_HPS_CORE2 | Supply power to HPS A76 Core2. | |
FPGA/HPS | VCCL_HPS_CORE3 | Supply power to HPS A76 Core3. | |
FPGA/SDM | VCC_IO_SDM | SDM block I/O digital supply voltage sense. | |
FPGA/SDM | VCCL_ADC_SDM | HPS DSU and periphery voltage sense. | |
FPGA/SDM | VCCL_SDM | SDM block I/O digital supply voltage sense. | |
FPGA/SDM | VCCPLLDIG_SDM | HPS DSU and periphery voltage sense. | |
FPGA/SDM | VCCH_SDM | P1V0_GR1 | Voltage rail sense. It can be 0.8 V/0.78 V/0.75 V according to the speed grade, and can be combined with VCCL_SDM for the devices without GTS transceiver. |
FPGA | VCCPT | P1V8_GR2a | Power supply for the IOPLL, programmable power technology, and I/O pre-drivers. |
FPGA/HVIO | VCCPT_HVIO | Pre-driver analog power supply pin for HVIO. | |
FPGA/SDM | VCCIO_SDM | Configuration pins power supply. | |
FPGA/HPS | VCCIO_HPS | The HPS dedicated I/Os support 1.8 V voltage level. | |
FPGA/SDM | VCCFUSEWR_SDM | The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Agilex™ Security architecture. | |
FPGA/HPS | VCCPLL1_HPS | VCCPLL1_HPS: Supply analog power to the main HPS PLLs. | |
VCCPLL2_HPS | VCCPLL2_HPS: Supply analog power to the peripheral HPS PLLs. | ||
FPGA/SDM | VCCADC | ADC power pin for the voltage sensors. | |
FPGA/SDM | VCCPLL_SDM | VCCPLL_SDM supplies analog power to the SDM block PLLs. | |
FPGA/PIO | VCCIO_PIO_T/B | P1V2_GR2b | Power supply voltage pins for the I/O banks. |
FPGA/SDM | VCCIO_PIO_SDM | VCCIO_PIO voltage rail sense line. | |
FPGA | VCCRCORE | Transceiver core power supply. | |
FPGA/HVIO | VCCIO_HVIO | P3V3/2V5/1V8_GR2b | Buffer analog power supply pin for HVIO. |
FPGA/SDM | VCCBAT | VCCBAT | Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register. |
PTC Rail Name | Board Connections | SystemConnections |
---|---|---|
VCC_HSSI | P0V8_GR1 | SmartVID devices, GTS transceiver digital logic power supply. |
VCC_HSSI | VCCL 0.8 V/0.78 V/0.75 V | Non-SmartVID devices, GTS transceiver digital logic power supply. |
VCCERT_GTS | P1V0_GR1 | GTS transceiver analog 1.0 V logic power pins. |
VCCEHT_GTS | P1V8_GR2a | GTS transceiver high-voltage analog power supply pins. |