General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public

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2.4.2.1. True Differential Signaling I/O Standard On-Chip Termination

All I/O pins and dedicated clock input pins located in the HSIO banks of Agilex™ 5 devices support on-chip differential termination (RD OCT). The Agilex™ 5 devices provide a 100 Ω on-chip differential termination option on each differential receiver channel for the True Differential Signaling, DPHY, and SLVS-400 I/O standards.
Figure 18. OCT for Differential I/O Termination