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1. Agilex™ 5 General-Purpose I/O Overview
2. Agilex™ 5 HSIO Banks
3. Agilex™ 5 HVIO Banks
4. Agilex™ 5 HPS I/O Banks
5. Agilex™ 5 SDM I/O Banks
6. Agilex™ 5 I/O Troubleshooting Guidelines
7. GPIO Intel® FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused HSIO Banks
2.5.14. HSIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for HSIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
7.1. Release Information for GPIO Intel® FPGA IP
7.2. Generating the GPIO Intel® FPGA IP
7.3. GPIO Intel® FPGA IP Parameter Settings
7.4. GPIO Intel® FPGA IP Interface Signals
7.5. GPIO Intel® FPGA IP Architecture
7.6. Verifying Resource Utilization and Design Performance
7.7. GPIO Intel® FPGA IP Timing
7.8. GPIO Intel® FPGA IP Design Examples
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2.4.1.2. OCT Calibration Block
You can calibrate the OCT using the OCT calibration block available in each HSIO bank. Only the 1.05 V, 1.1 V, and 1.2 V VCCIO_PIO banks can use the OCT calibration block.
The OCT calibration block can calibrate the I/O buffers located in the same HSIO banks only, except for DDR4 or DDR5 DIMM implementation. Examples:
- Non-DDR4 and non-DDR5 DIMM implementation—you can use the OCT calibration block in bank 2A to calibrate the I/O buffers in bank 2A only.
- DDR4 or DDR5 DIMM implementation that spans across banks 2A and 2B—you can use the OCT calibration block in either bank to calibrate the DDR4 or DDR5 DIMM I/O buffers in both banks.
The OCT calibration process uses the RZQ pin that is available in every HSIO sub-bank for series-calibrated and parallel-calibrated terminations.
- You can use the RZQ pin in one sub-bank to calibrate I/Os in the other sub-bank within the same HSIO bank. For example, you can use the RZQ pin in the bottom index sub-bank of bank 2B to calibrate the I/Os in the top index sub-bank of bank 2B. Both sub-bank must use the same VCCIO_PIO voltage value.
- The RZQ pin is a dual-purpose I/O pin and functions as a general-purpose I/O pin if you do not use the calibration circuit.
- The RZQ pin shares the same VCCIO_PIO supply voltage with the I/O sub-bank where the pin is located.
The OCT calibration block has an external 240 Ω reference resistor associated with it through the RZQ pin available in every sub-bank.
- Connect the RZQ pin to GND through an external 240 Ω resistor.
- For differential I/O standards, you must use the same RZQ resistor to calibrate both the positive and negative legs of the differential I/O pin.
- You can use each RZQ resistor to calibrate two RS OCT settings and one RT OCT setting for all I/O standards.