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1. Agilex™ 5 General-Purpose I/O Overview
2. Agilex™ 5 HSIO Banks
3. Agilex™ 5 HVIO Banks
4. Agilex™ 5 HPS I/O Banks
5. Agilex™ 5 SDM I/O Banks
6. Agilex™ 5 I/O Troubleshooting Guidelines
7. GPIO Intel® FPGA IP
8. Programmable I/O Features Description
9. Document Revision History for the General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os
2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent HSIO Bank
2.5.3. VREF Sources and Input Standards Grouping
2.5.4. HSIO Pin Restrictions for External Memory Interfaces
2.5.5. RZQ Pin Requirement
2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages
2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check
2.5.8. Simultaneous Switching Noise
2.5.9. HPS Shared I/O Requirements
2.5.10. Clocking Requirements
2.5.11. SDM Shared I/O Requirements
2.5.12. Unused Pins
2.5.13. VCCIO_PIO Supply for Unused HSIO Banks
2.5.14. HSIO Pins During Power Sequencing
2.5.15. Drive Strength Requirement for HSIO Input Pins
2.5.16. Maximum DC Current Restrictions
2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
1.2 V LVCMOS I/O Standard Voltage Swing Calculation
1.2 V Voltage-Referenced I/O Standards Voltage Swing Calculation
2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration
2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements
2.5.20. Implementing a Pseudo Open Drain
2.5.21. Allowed Duration for Using RT OCT
2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.5.23. Implementing SLVS-400 or DPHY I/O Standard with 1.1 V VCCIO_PIO
7.1. Release Information for GPIO Intel® FPGA IP
7.2. Generating the GPIO Intel® FPGA IP
7.3. GPIO Intel® FPGA IP Parameter Settings
7.4. GPIO Intel® FPGA IP Interface Signals
7.5. GPIO Intel® FPGA IP Architecture
7.6. Verifying Resource Utilization and Design Performance
7.7. GPIO Intel® FPGA IP Timing
7.8. GPIO Intel® FPGA IP Design Examples
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2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility
Evaluate the electrical signal level compatibility between Agilex™ 5 1.05 V, 1.1 V, or 1.2 V output and the downstream device. Ensure that the VOH and VOL voltages of the 1.05 V, 1.1 V, or 1.2 V output buffer conform to the VIH and VIL specifications of the receiving buffer of the downstream device.
1.2 V LVCMOS I/O Standard Voltage Swing Calculation
If you use the 1.2 V LVCMOS I/O standard, the output signal swings from 0 V to 1.2 V on a lossless transmission line with no external pull-up or pull-down component. Ensure that the VIH or VIL tolerance of the downstream connecting device can meet those conditions.
1.2 V Voltage-Referenced I/O Standards Voltage Swing Calculation
If you use the 1.2 V voltage-referenced I/O standards, the output signal swing has a dependency on the external board termination or the internal termination of the receiver.
Figure 22. Termination Setup Using 40 Ω RS OCT Driver with On-Board 50 Ω Pull-Up Resistor to VCCIO_PIO/2 This figure shows an example termination setup and its equivalent circuit.
Figure 23. Equivalent Circuit of the Example with Output Buffer Driving HIGHWhen the output buffer is driving HIGH, the pin voltage is 0.93 V based on voltage divider rule: ( ).
Figure 24. Equivalent Circuit of the Example with Output Buffer Driving LOWWhen the output buffer is driving LOW, the pin voltage is 0.27 V based on the voltage divider rule: ( ).