General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public

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2.4.2.1.2. Guidelines: Differential Input RD OCT

Disable RD OCT for interfaces that require external voltage bias circuitry near the true differential receivers of Agilex™ 5 devices.
Figure 19. External Voltage Bias Circuitry with RD OCT Disabled