General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs

ID 813934
Date 4/05/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.5.1.2. Output and Output Enable Paths

The output delay element sends data to the pad through the output buffer.
Figure 41. Simplified View of Single-Ended HSIO Output Path


Figure 42. Output Path Waveform in DDIO Mode
Figure 43.  Simplified View of Output Enable Path


The difference between the output path and output enable (OE) path is that the OE path does not contain DDIO. To support packed-register implementations in the OE path, a simple register operates as DDIO.