Visible to Intel only — GUID: sss1441694013315
Ixiasoft
Visible to Intel only — GUID: sss1441694013315
Ixiasoft
3.1.3. The AVST_READY Signal
If you use the Parallel Flash Loader II Intel® FPGA IP as the configuration host, the AVST_READY synchronizer logic is included.
The AVST_READY signal sent by the Agilex™ 5 device to the host is not synchronized with the AVSTx8_CLK or AVST_CLK. To configure the Agilex™ 5 device successfully, the host must adhere to the following constraints:
- The host must drive no more than six data words after the deassertion of the AVST_READY signal including the delay incurred by the 2-stage register synchronizer.
- The host must synchronize the AVST_READY signal to the AVST_CLK signal using a 2-stage register synchronizer. Here is a Register transfer level (RTL) example code for 2-stage register synchronizer:
always @(posedge avst_clk or negedge reset_n) begin if (~reset_n) begin fpga_avst_ready_reg1 <= 0; fpga_avst_ready_reg2 <= 0; else fpga_avst_ready_reg1 <= fpga_avst_ready; fpga_avst_ready_reg2 <= fpga_avst_ready_reg1; end end
Where:- The AVST_CLK signal comes from either Parallel Flash Loader II Intel® FPGA IP or your Avalon® -ST controller logic.
- fpga_avst_ready is the AVST_READY signal from the Agilex™ 5 device.
- fpga_avst_ready_reg2 signal is the AVST_READY signal that is synchronous to AVST_CLK.
Optionally, you can monitor the CONF_DONE signal to indicate the flash has sent all the data to FPGA or to indicate the configuration process is complete.
If you use the Parallel Flash Loader II Intel® FPGA IP as the configuration host, you can use the Quartus® Prime software to store the binary configuration data to the flash memory through the Parallel Flash Loader II Intel® FPGA IP.
If you use the Avalon-ST Adapter IP core as part of the configuration host, set the Source Ready Latency value between 1- 6.
Avalon-ST x8 configuration scheme uses the SDM pins only. Avalon-ST x16 configuration scheme only uses dual-purpose I/O pins that you can use as general-purpose I/O pins after configuration.