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1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Agilex™ 5 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and GTS Transceivers
2.5. Agilex™ 5 Configuration Pins
2.6. Configuration Clocks
2.7. Agilex™ 5 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
Create a FLASH_CLK clock
Set output delay for output pins
Set input delay for input pins
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 5 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
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3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
Create a FLASH_CLK clock
Example below assigns CFI flash clock pin (flash_clk) to the flash clock. You constrain the flash_clk pin only when using burst mode.
create_generated_clock -name FLASH_CLK -source [get_ports {clk_50m_max5}] [get_ports {flash_clk}]
Set output delay for output pins
Example below sets the output delay for CFI flash output pins.
set flash_data_tracemax 0.250 set flash_data_tracemin 0.000 set flash_clk_tracemax 0.250 set flash_clk_tracemin 0.000 set flash_Tsu 3.500 set flash_Th 2.000 set flash_out_max_dly [expr $flash_data_tracemax + $flash_Tsu - $flash_clk_tracemin] set flash_out_min_dly [expr $flash_data_tracemin - $flash_Th - $flash_clk_tracemax] #Note: For normal mode, the clock is referred to input pfl_clk clock(clk_50m_max5) of PFL II IP. #If burst mode is used, the clock is referred to flash clock of PFL II IP. set_output_delay -add_delay -max -clock [get_clocks {clk_50m_max5}] \ $flash_out_max_dly [get_ports {flash_nce[0] flash_nce[1] flash_noe flash_nwe flash_addr[*] flash_data[*]}] set_output_delay -add_delay -min -clock [get_clocks {clk_50m_max5}] \ $flash_out_min_dly [get_ports { flash_nce[0] flash_nce[1] flash_noe flash_nwe flash_addr[*] flash_data[*]}] #Only need to constraint flash_advn pin when using burst mode. set_output_delay -add_delay -max -clock [get_clocks { FLASH_CLK }] $flash_out_max_dly [get_ports {flash_nadv}] set_output_delay -add_delay -min -clock [get_clocks { FLASH_CLK }] $flash_out_min_dly [get_ports {flash_nadv}]
Set input delay for input pins
Example below sets the input delay for CFI flash data.
# For Normal Mode set flash_noe_tracemax 0.250 set flash_noe_tracemin 0.000 set flash_tco_max 7.000 set flash_tco_min 0.000 set normal_in_max_dly [expr $flash_data_tracemax + $flash_tco_max + $ flash_noe_tracemax] set normal_in_min_dly [expr $flash_data_tracemin + $flash_tco_min + $ flash_noe_tracemin] set_input_delay -clock { clk_50m_max5 } -max $normal_in_max_dly [get_ports {flash_data[*]}] set_input_delay -clock { clk_50m_max5 } -min $normal_in_min_dly [get_ports {flash_data[*]}]
# For Burst mode set flash_tco_max 5.500 set flash_tco_min 2.000 set burst_in_max_dly [expr $flash_data_tracemax + $flash_tco_max + $flash_clk_tracemax] set burst_in_min_dly [expr $flash_data_tracemin + $flash_tco_min + $flash_clk_tracemin] set_input_delay -clock { FLASH_CLK } -max $burst_in_max_dly [get_ports {flash_data[*]}] set_input_delay -clock { FLASH_CLK } -min $burst_in_min_dly [get_ports {flash_data[*]}]