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Ixiasoft
2.4. Additional Clock Requirements for HPS and GTS Transceivers
FPGA Configuration
The Agilex™ 5 device requires additional clocks for HPS, HPS EMIF IP and GTS transceiver. You must provide a free-running, stable reference clock to these blocks before configuration begins. The clock frequencies must match the frequency settings specified in the Quartus® Prime software during configuration. These reference clocks are in addition to the configuration clock requirements for an internal or external oscillator described in OSC_CLK_1 Requirements.
Quartus® Prime Pro Edition software allows you to configure the HPS prior to FPGA configuration. To enable this option, select HPS First in the Assignments > Device > Device and Pin Options > Configuration > HPS/FPGA Configuration order dialog box.
HPS First Configuration
Agilex™ 5 devices have the option of booting the HPS before configuring the FPGA core logic. This method is known as the HPS first configuration. When you choose this option in the Quartus® Prime Pro Edition software, the following clocks must be operational prior to the FPGA I/O, HPS I/O, and HPS boot, also called a phase 1 configuration.
Block | Clock name |
---|---|
HPS reference clock | HPS_OSC_CLK |
HPS EMIF | pll_ref_clk |
The remaining clocks specified in the FPGA Configuration must be fully operational prior the FPGA core logic configuration, also called phase 2 configuration.