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1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Agilex™ 5 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and GTS Transceivers
2.5. Agilex™ 5 Configuration Pins
2.6. Configuration Clocks
2.7. Agilex™ 5 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
Set a false path for Parallel Flash Loader II Intel® FPGA IP input pins
Set input delay to Parallel Flash Loader II Intel® FPGA IP input pins
Set a false path for fpga_pgm[] input pin
Set input delay to pfl_nreconfigure input pin
Set input delay to pfl_reset_watchdog pin
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 5 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
Visible to Intel only — GUID: otp1621533765284
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3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
Set a false path for Parallel Flash Loader II Intel® FPGA IP input pins
You can set the pfl_nreset input reset pin to a false path since this pin is asynchronous.
set_false_path -from [get_ports {pfl_nreset}] -to *
Set input delay to Parallel Flash Loader II Intel® FPGA IP input pins
Example below sets the input delay for the pfl_flash_access_granted pin.
- You don't have to constraint the path when you use the device arbiter logic to control the pin,
- You don't have to constraint the path when not using the device arbiter logic or the external processor to control the pin and you loopback the pfl_flash_access_request signal to the pfl_flash_access_granted pin.
- You can constraint the path when a processor or an external device controls the pfl_flash_access_granted pin.
set_input_delay -clock {clk_50m_sysmax} -max [<pfl_flash_access_granted_tco_max> + <pfl_flash_access_granted_tracemax>] [get_ports {pfl_flash_access_granted}] set_input_delay -clock {clk_50m_sysmax} -min [<pfl_flash_access_granted_tco_min> + <pfl_flash_access_granted_tracemin>] [get_ports {pfl_flash_access_granted}]
Set a false path for fpga_pgm[] input pin
You can set a false path to quasi-static signals such as reset and configuration signals (fpga_conf_done, fpga_nstatus) that are stable for a long periods of time.
set_false_path -from [get_ports {fpga_pgm[]}] -to *
Set input delay to pfl_nreconfigure input pin
If you use the external component to drive this pin, you must set the input delay path to drive the pfl_nreconfigure pin.
set_input_delay -clock {clk_50m_sysmax} -max [<pfl_nreconfigure_tco_max> + <pfl_nreconfigure_tracemax>] \ [get_ports {pfl_nreconfigure}] set_input_delay -clock {clk_50m_sysmax} -min [<pfl_nreconfigure_tco_min> + <pfl_nreconfigure_tracemin>] \ [get_ports {pfl_nreconfigure}]
Set input delay to pfl_reset_watchdog pin
If you use the external component to drive this pin, you must set the input delay path to drive the pfl_reset_watchdog pin.
set_input_delay -clock {clk_50m_sysmax} -max [$pfl_reset_watchdog_tco_max + $pfl_reset_watchdog_tracemax] \ [get_ports {pfl_nreconfigure}] set_input_delay -clock {clk_50m_sysmax} -min [$pfl_reset_watchdog_tco_min + $pfl_reset_watchdog_tracemin] \ [get_ports {pfl_nreconfigure}]