Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813773
Date 7/24/2024
Public
Document Table of Contents
Document Table of Contents x
1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs 2. Agilex™ 5 Configuration Details 3. Agilex™ 5 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Agilex™ 5 Configuration Features 7. Agilex™ 5 Debugging Guide 8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs x
1.1. Agilex™ 5 Configuration Overview 1.2. Agilex™ 5 Configuration Architecture
1.1. Agilex™ 5 Configuration Overview x
1.1.1. Configuration and Related Signals 1.1.2. Intel Download Cables Supporting Configuration in Agilex™ 5 Devices
1.2. Agilex™ 5 Configuration Architecture x
1.2.1. Secure Device Manager
1.2.1. Secure Device Manager x
1.2.1.1. Updating the SDM Firmware 1.2.1.2. Specifying Boot Order for Agilex™ 5 SoC Devices
2. Agilex™ 5 Configuration Details x
2.1. Agilex™ 5 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS and GTS Transceivers 2.5. Agilex™ 5 Configuration Pins 2.6. Configuration Clocks 2.7. Agilex™ 5 Configuration Time Estimation 2.8. Generating Compressed .sof File
2.5. Agilex™ 5 Configuration Pins x
2.5.1. SDM Pin Mapping 2.5.2. MSEL Settings 2.5.3. Device Configuration Pins for Optional Configuration Signals
2.5.3. Device Configuration Pins for Optional Configuration Signals x
2.5.3.1. Specifying Optional Configuration Pins 2.5.3.2. Enabling Dual-Purpose Pins 2.5.3.3. I/O Standards and Features for Configuration Pins 2.5.3.4. SDM I/O Pins for Power Management and SmartVID 2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)
2.5.3.1. Specifying Optional Configuration Pins x
2.5.3.1.1. nCONFIG 2.5.3.1.2. nSTATUS 2.5.3.1.3. CONF_DONE and INIT_DONE 2.5.3.1.4. SDM_IO Pins
2.5.3.3. I/O Standards and Features for Configuration Pins x
2.5.3.3.1. IBIS Model
2.6. Configuration Clocks x
2.6.1. Setting Configuration Clock Source 2.6.2. OSC_CLK_1 Clock Input
3. Agilex™ 5 Configuration Schemes x
3.1. Avalon-ST Configuration 3.2. AS Configuration 3.3. JTAG Configuration
3.1. Avalon-ST Configuration x
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II) x
3.1.7.1. Functional Description 3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration 3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP 3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP 3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP 3.1.7.6. Supported Flash Memory Devices
3.1.7.1. Functional Description x
3.1.7.1.1. Generating and Programming a .pof into CFI Flash 3.1.7.1.2. Implementing Multiple Pages in the Flash .pof 3.1.7.1.3. Storing Option Bits 3.1.7.1.4. Verifying the Option Bit Start and End Addresses 3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration x
3.1.7.2.1. Parallel Flash Loader II Intel® FPGA IP Parameters 3.1.7.2.2. Parallel Flash Loader II Intel® FPGA IP Signals
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP 3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address 3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration 3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins 3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash 3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash 3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins 3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP x
3.1.7.5.1. Converting .sof to .pof File 3.1.7.5.2. Programming CPLDs and Flash Memory Devices Sequentially 3.1.7.5.3. Programming CPLDs and Flash Memory Devices Separately 3.1.7.5.4. Defining New CFI Flash Memory Device
3.2. AS Configuration x
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Skew Tolerance Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme Debugging Suggestions
3.2.5. Skew Tolerance Guidelines x
3.2.5.1. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.5.2. Maximum Allowable External nCSO Pin Skew Delay Guidelines
3.2.6. Programming Serial Flash Devices x
3.2.6.1. Programming Serial Flash Devices using the AS Interface 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface
3.2.7. Serial Flash Memory Layout x
3.2.7.1. Understanding Quad SPI Flash Byte-Addressing
3.2.10. Quartus® Prime Programming Steps x
3.2.10.1. Generating Programming Files using the Programming File Generator 3.2.10.2. Programming .pof files into Serial Flash Device 3.2.10.3. Programming .jic files into Serial Flash Device
3.3. JTAG Configuration x
3.3.1. JTAG Configuration Scheme Hardware Components and File Types 3.3.2. JTAG Device Configuration 3.3.3. JTAG Multi-Device Configuration 3.3.4. Debugging Guidelines for the JTAG Configuration Scheme
3.3.2. JTAG Device Configuration x
3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections 3.3.2.2. JTAG Single-Device Configuration using a Microprocessor
3.3.3. JTAG Multi-Device Configuration x
3.3.3.1. JTAG Multi-Device Configuration using Download Cable
4. Including the Reset Release Intel® FPGA IP in Your Design x
4.1. Understanding the Reset Release IP Requirement 4.2. Instantiating the Reset Release IP In Your Design 4.3. Gating the PLL Reset Signal 4.4. Guidance When Using Partial Reconfiguration (PR) 4.5. Detailed Description of Device Configuration
4.5. Detailed Description of Device Configuration x
4.5.1. Device Initialization 4.5.2. Embedded Memory Block Initial Conditions 4.5.3. Protecting State Machine Logic
5. Remote System Update (RSU) x
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example
5.1. Remote System Update Functional Description x
5.1.1. RSU Glossary 5.1.2. Remote System Update Using AS Configuration 5.1.3. Remote System Update Configuration Images 5.1.4. Remote System Update Configuration Sequence 5.1.5. RSU Recovery from Corrupted Images 5.1.6. Updates with the Factory Update Image
5.3. Commands and Responses x
5.3.1. Operation Commands 5.3.2. Error Code Responses 5.3.3. Error Code Recovery
5.4. Quad SPI Flash Layout x
5.4.1. High Level Flash Layout 5.4.2. Detailed Quad SPI Flash Layout
5.4.1. High Level Flash Layout x
5.4.1.1. Standard (non-RSU) Image Layout in Flash 5.4.1.2. RSU Image Layout in Flash – SDM Perspective 5.4.1.3. RSU Image Layout – Your Perspective
5.4.1.2. RSU Image Layout in Flash – SDM Perspective x
5.4.1.2.1. Firmware Version Information
5.4.2. Detailed Quad SPI Flash Layout x
5.4.2.1. RSU Image Sub-Partitions Layout 5.4.2.2. Sub-Partition Table Layout 5.4.2.3. Configuration Pointer Block Layout 5.4.2.4. Modifying the List of Application Images
5.5. Generating Remote System Update Image Files Using the Programming File Generator x
5.5.1. Generating the Initial RSU Image 5.5.2. Generating an Application Image 5.5.3. Generating a Factory Update Image 5.5.4. Command Sequence To Perform Quad SPI Operations
5.5.1. Generating the Initial RSU Image x
5.5.1.1. Generating the Initial RSU Image Using SOF Files 5.5.1.2. Generating the Initial RSU Image Using RBF Files
5.6. Remote System Update from FPGA Core Example x
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
6. Agilex™ 5 Configuration Features x
6.1. Device Security 6.2. Configuration via Protocol 6.3. Partial Reconfiguration
7. Agilex™ 5 Debugging Guide x
7.1. Configuration Debugging Checklist 7.2. Agilex™ 5 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. Configuration File Format Differences 7.5. Understanding SEUs 7.6. Reading the Unique 64-Bit CHIP ID 7.7. Understanding and Troubleshooting Configuration Pin Behavior 7.8. Configuration Debugger Tool 7.9. CRAM Integrity Check Feature
1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

3.2.11. Debugging Guidelines for the AS Configuration Scheme

The AS configuration scheme operation is like earlier device families. However, there is one significant difference. Agilex™ 5 devices using AS mode, try to load a firmware section from addresses 0, 512k, 1024k and 1536k in the serial flash device connected to the CS0 pin.

If the configuration bitstream does not include a valid image, the SDM asserts an error by driving nSTATUS low. You can recover from the error by reconfiguring the FPGA over JTAG, or by driving nCONFIG low.

When the device powers on with MSEL set to JTAG, the SDM tristates the AS pins, AS_CLK, AS_nRST, AS_DATA0-AS_DATA3, and AS_nCSO0-AS_nCSO3. If MSEL is either AS fast or normal, the SDM drives the AS pins until you power cycle the Agilex™ 5 device. Unlike earlier device families, the AS pins are not tristated when the device enters user mode.

The AS configuration scheme has power-on requirements. If you use AS Fast mode, you must ramp all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the AS x4 device is within its operating voltage range when the Agilex™ 5 device begins accessing the AS x4 device.

When using AS fast mode, all power supplies to the Agilex™ 5 device must be fully ramped-up to the recommended operating conditions before the SDM releases from reset. To meet the PCIe* power-up-to-active time requirement for CvP, all the power supplies to the Agilex™ 5 device must be at the recommended operating range within 10 ms.

Debugging Suggestions

Here are some debugging tips for the AS configuration scheme:

  • Ensure that the design meets the power-supply ramp requirements for fast AS mode. If using fast mode, all power supplies must ramp to the recommended operating condition within 10 ms.
  • Ensure that the flash is powered up and ready to be accessed when the Agilex™ 5 device exits power-on reset.
  • If you are using an external clock source for configuration, ensure the OSC_CLK_1 pin is fed correctly, and the frequency matches the frequency you set for the OSC_CLK_1 in your Quartus® Prime Pro Edition project.
  • Ensure the MSEL pins reflect the correct AS configuration scheme.
  • If the AS configuration is failing due to a corrupt image inside the QSPI flash device and reprogramming does not resolve the problem, you have two possible solutions depending on the components you are using for configuration:
    • If you are using a third-party programmer to configure the flash directly from an AS or JTAG header as shown in AS Programming Using Quartus® Prime or Third-Party Programmer change the MSEL setting to JTAG. Setting MSEL to JTAG prevents the corrupt image from loading automatically at power-on. Then, update the image in the QSPI flash device through the AS or JTAG header.
    • If you are programming the flash device using the JTAG header as shown in Programming Your Serial Configuration Device Using JTAG, force the nCONFIG signal to low. When nCONFIG is low, the image cannot load from the QSPI flash device. Then, update the image in quad serial flash through the JTAG header.
  • If you are using AS x4 flash memories with AS Fast mode, you must ramp up all power supplies to the recommended operating condition within 10 ms. This ramp-up requirement ensures that the QSPI flash device is within its operating voltage range when the Agilex™ 5 device begins to access it.
  • Check endianness of the .rpd if using a third-party programmer to program the QSPI flash device. You should generate the .rpd as big endian.
  • If you are using the OSC_CLK_1 clock source for configuration, ensure OSC_CLK_1 is free running and stable before SDM starts to load a bitstream from the Quad SPI device. The SDM starts configuration after the device exits the POR state if nCONFIG is held high.
  • Try a lower AS clock frequency setting.
  • If you drive nCONFIG signal using the external host, ensure it remains high during the AS x4 configuration scheme.
  • If you pulse nCONFIG low for reconfiguration, ensure that the nSTATUS acknowledges nCONFIG. If nSTATUS does not follow the nCONFIG signal, the FPGA may not exit power on reset state. You may need to power cycle the PCB.
  • Ensure no external component drives the nSTATUS signal low during the power up.
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