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1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Agilex™ 5 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and GTS Transceivers
2.5. Agilex™ 5 Configuration Pins
2.6. Configuration Clocks
2.7. Agilex™ 5 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 5 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
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2.7. Agilex™ 5 Configuration Time Estimation
This section describes configuration time for various configuration modes for different bitstream sizes. For timing dependent software systems, configuration may be required to complete in a specified amount of time, for example, to successfully configure PCIe* , the Agilex™ 5 device is required to enter user mode in less than 1 second to be valid. Use the values referenced below to determine the configuration mode that best suits your design and timing requirements.
The table provides time estimates for the full FPGA configuration only. In HPS-enabled designs, the table also considers the FPGA configuration first mode. Note that the HPS boot first mode in HPS-enabled designs is not considered. Also, the CvP periphery image configuration is not considered.
The following conditions were used to estimate the configuration time values:
- VID mode of operation set to PMBus Master
- Uses Intersil* ISL68223 regulator to regulate the PMBus
- Configuration clock source is OSC_CLK_1, with input reference clock frequency of 25 MHz, 100 MHz, or 125 MHz
- No advanced security features
- For AVST x8 or AVST x16 configuration modes, set the AVST_CLK to 125 MHz. The external host controller supplies the AVST_DATA by asserting the AVST_VALID signal high whenever the AVST_READY signal is high.
- For AS x4 configuration mode:
- Storage device is a 2 Gb Micron* QSPI flash memory device
- AS_CLK settings by speed grade:
-
- 166 MHz for Agilex™ 5 devices with speed grade -4S/-5S
- 100 MHz for Agilex™ 5 devices with speed grade -6S
Device | RBF File Size (MB) | Configuration Time Estimation (ms) | |||||
---|---|---|---|---|---|---|---|
AS x4 | AVST x8 | AVST x16 | |||||
-4S/-5S speed | -6S speed | -4S/-5S speed | -6S speed | -4S/-5S speed | -6S speed | ||
A5E 043 A5E 052 A5E 065 |
3.1 | 220 | 260 | 150 | 170 | 110 | 120 |
12.1 | 320 | 420 | 200 | 220 | 150 | 160 | |
15 | 350 | 470 | 220 | 230 | 160 | 170 |