Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs

ID 813773
Date 7/24/2024
Public
Document Table of Contents

2.7. Agilex™ 5 Configuration Time Estimation

This section describes configuration time for various configuration modes for different bitstream sizes. For timing dependent software systems, configuration may be required to complete in a specified amount of time, for example, to successfully configure PCIe* , the Agilex™ 5 device is required to enter user mode in less than 1 second to be valid. Use the values referenced below to determine the configuration mode that best suits your design and timing requirements.

The table provides time estimates for the full FPGA configuration only. In HPS-enabled designs, the table also considers the FPGA configuration first mode. Note that the HPS boot first mode in HPS-enabled designs is not considered. Also, the CvP periphery image configuration is not considered.

The following conditions were used to estimate the configuration time values:
  • VID mode of operation set to PMBus Master
  • Uses Intersil* ISL68223 regulator to regulate the PMBus
  • Configuration clock source is OSC_CLK_1, with input reference clock frequency of 25 MHz, 100 MHz, or 125 MHz
  • No advanced security features
  • For AVST x8 or AVST x16 configuration modes, set the AVST_CLK to 125 MHz. The external host controller supplies the AVST_DATA by asserting the AVST_VALID signal high whenever the AVST_READY signal is high.
  • For AS x4 configuration mode:
    • Storage device is a 2 Gb Micron* QSPI flash memory device
    • AS_CLK settings by speed grade:
      • 166 MHz for Agilex™ 5 devices with speed grade -4S/-5S
      • 100 MHz for Agilex™ 5 devices with speed grade -6S
Table 17.  Configuration Time for Various Configuration Modes The configuration file size is dependent on the user design complexity. In general, higher logic utilization with randomized logic patterns produces larger configuration file sizes. Regardless of the configuration file size, the decompression block must decompress the bitstream and configure the same number of CRAM bits within the device. A higher bandwidth configuration scheme like in the AVST x16 may send larger configuration files in shorter time. However, there is little to no benefit with sending a small configuration file when using higher bandwidth configuration schemes as the bottleneck is the time taken for decompression and not the time taken to send over the bitstream to the device. The data in this table is preliminary.
Device RBF File Size (MB) Configuration Time Estimation (ms)
AS x4 AVST x8 AVST x16
-4S/-5S speed -6S speed -4S/-5S speed -6S speed -4S/-5S speed -6S speed

A5E 043

A5E 052

A5E 065
3.1 220 260 150 170 110 120
12.1 320 420 200 220 150 160
15 350 470 220 230 160 170