Visible to Intel only — GUID: sss1466478401834
Ixiasoft
1. Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2. Agilex™ 5 Configuration Details
3. Agilex™ 5 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Agilex™ 5 Configuration Features
7. Agilex™ 5 Debugging Guide
8. Document Revision History for the Device Configuration User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Agilex™ 5 Configuration Timing Diagram
2.2. Configuration Flow Diagram
2.3. Device Response to Configuration and Reset Events
2.4. Additional Clock Requirements for HPS and GTS Transceivers
2.5. Agilex™ 5 Configuration Pins
2.6. Configuration Clocks
2.7. Agilex™ 5 Configuration Time Estimation
2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types
3.1.2. Enabling Avalon-ST Device Configuration
3.1.3. The AVST_READY Signal
3.1.4. RBF Configuration File Format
3.1.5. Avalon-ST Single-Device Configuration
3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Parallel Flash Loader II Intel® FPGA IP (PFL II)
3.1.7.1. Functional Description
3.1.7.2. Designing with the Parallel Flash Loader II Intel® FPGA IP for Avalon-ST Single Device Configuration
3.1.7.3. Generating the Parallel Flash Loader II Intel® FPGA IP
3.1.7.4. Constraining the Parallel Flash Loader II Intel® FPGA IP
3.1.7.5. Using the Parallel Flash Loader II Intel® FPGA IP
3.1.7.6. Supported Flash Memory Devices
3.1.7.3.1. Controlling Avalon-ST Configuration with Parallel Flash Loader II Intel® FPGA IP
3.1.7.3.2. Mapping Parallel Flash Loader II Intel® FPGA IP and Flash Address
3.1.7.3.3. Creating a Single Parallel Flash Loader II Intel® FPGA IP for Programming and Configuration
3.1.7.3.4. Creating Separate Parallel Flash Loader II Intel® FPGA IP Functions
3.1.7.4.1. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints to FPGA Avalon-ST Pins
3.1.7.4.2. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for Using QSPI Flash
3.1.7.4.3. Parallel Flash Loader II Intel® FPGA IP Recommended Design Constraints for using CFI Flash
3.1.7.4.4. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Input Pins
3.1.7.4.5. Parallel Flash Loader II Intel® FPGA IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types
3.2.2. AS Single-Device Configuration
3.2.3. AS Using Multiple Serial Flash Devices
3.2.4. AS Configuration Timing Parameters
3.2.5. Skew Tolerance Guidelines
3.2.6. Programming Serial Flash Devices
3.2.7. Serial Flash Memory Layout
3.2.8. AS_CLK
3.2.9. Active Serial Configuration Software Settings
3.2.10. Quartus® Prime Programming Steps
3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description
5.2. Guidelines for Performing Remote System Update Functions for Non-HPS
5.3. Commands and Responses
5.4. Quad SPI Flash Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator
5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites
5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
5.6.3. Programming Flash Memory with the Initial Remote System Update Image
5.6.4. Reconfiguring the Device with an Application or Factory Image
5.6.5. Adding an Application Image
5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist
7.2. Agilex™ 5 Configuration Architecture Overview
7.3. Understanding Configuration Status Using quartus_pgm command
7.4. Configuration File Format Differences
7.5. Understanding SEUs
7.6. Reading the Unique 64-Bit CHIP ID
7.7. Understanding and Troubleshooting Configuration Pin Behavior
7.8. Configuration Debugger Tool
7.9. CRAM Integrity Check Feature
Visible to Intel only — GUID: sss1466478401834
Ixiasoft
2.5.3.2. Enabling Dual-Purpose Pins
AVST_CLK, AVST_DATA[15:0], and AVST_VALID are dual-purpose pins. Once the device enters user mode these pins can function either as GPIOs or as tri-state inputs.
If you use these pins as GPIOs, make the following assignments:
- Set VCCIO of the I/O bank at 1.2 V
- Assign the 1.2 V I/O standard to these pins
Complete the following steps to assign these settings to the dual-purpose pins:
- On the Assignments menu, click Device.
- In the Device and Pin Options dialog box, select the Dual-Purpose Pins category.
- In the Dual-purpose pins table, set the pin functionality in the Value column.
Figure 13. Enabling Dual-Purpose Pins
- Click OK to confirm and close the Device and Pin Options
Attention: When you use the Avalon® -ST configuration scheme the dual-purpose Avalon® -ST pins have the following restrictions:
- You cannot use the Avalon® -ST interface for partial reconfiguration (PR).
- AVSTx16 configuration scheme cannot be used in designs that include the HPS. HPS-EMIF signals and AVSTx16 signals are both located in the same bank, therefore, they cannot be used simultaneously. The AVSTx8 mode uses dedicated SDM I/O pins, therefore can be used in designs that include the HPS.
- In designs that do not include the HPS, you can use dual purpose AVST pins after entering user mode, with the restrictions listed in the following table.
Table 9. Dual-Purpose Pin Restrictions for Avalon Streaming x16 Configuration Scheme Dual-Purpose Pin Avalon Streaming x16 Not Used in User Mode Used in User Mode AVST_CLK Setting: As input tri-stated Setting: Set as regular I/O Pin Connection: Set as Input and assign ALL pins in pin assignment
AVST_VALID AVST_DATA[15:0] Note:- All pins in the same group name must be assigned to the physical pin in pin assignment. For instance, if only 2 out of 16 pins from AVST_DATA[15:0] are used, then all 16 pins must be assigned to physical pins including the unused pins in the user design.
- All pins with pin assignments must be in known state, whether weak pull-up or weak pull-down.