6.4.2.5. HPS IO Hash Mismatch Troubleshooting Examples for HPS EMIF IOs
The following table shows HPS IO hash mismatch troubleshooting examples.
| Exercise | Differences between Design 1 and Design 2 | IO Hash Difference Adjustment |
|---|---|---|
| IO Configuration Differences on HPS EMIF IPs and non-HPS EMIF IPs | ||
| IO HPS EMIF configuration | In design 1, the IO HPS EMIF IP has configuration A. In design 2, the IO HPS EMIF IP has configuration B. | IO HPS EMIF IP configuration differences cause IO hash to mismatch. Open the IO HPS EMIF Platform Designer IP and compare the IP parameters in the GUI to ensure they match between the two designs. |
| HPS EMIF IP placement | In both designs, the HPS EMIF IP is placed into the HPS IO banks. In design 2 only, a non-HPS EMIF IP is also placed into the HPS IO banks. | The IO hash mismatches because the HPS IO bank in design 2 is configured differently to accommodate the additional IPs. Check the Pin Planner and Chip Planner (or Interface Planner) to ensure the same set of cell locations is occupied in each design. |
| IO pin analog setting | An IO pin in HPS IO bank has different analog setting in each design. | The IO HPS bank hash mismatches due to inconsistent settings. To identify mismatched settings, check the analog settings columns in the "Input/Output Pins" sections of the compilation reports for both designs. |
| IO pin standard type | An IO pin placed into an HPS IO bank has different standard support type in each design. |
The IO supported standard defined in the designs differs, causing an IO hash difference. To fix the design, configure the IO pin to have the same IO standard in both designs. |
| Pin Location Differences | ||
| Non-HPS IP pins constrained | In design 1, all non-HPS EMIF IP pins are constrained. In design 2, some of these pins are unconstrained. | The IO hash might mismatch if unconstrained pins are placed in the HPS IO banks. Check the fitter report for "Missing location assignment" warnings. |
| Non-HPS IP pins constrained into IO HPS bank | In both designs, all non-HPS EMIF IP pins are constrained. However, some pins are placed in an HPS IO bank, and the pin placement might differ between the two designs. | The IO hash might mismatch if there are differences in pin placement within the HPS IO bank. Check the Pin Planner to ensure that all pins in the HPS IO banks have identical placements. |
| IO HPS EMIF IP pin placement | In both designs, the IO HPS EMIF IP has the same configuration, but the pin placement differs between the two designs. | Differences in the IO HPS EMIF IP pin placement within the HPS IO banks cause an IO hash mismatch. Open the Pin Planner and verify that all IO HPS EMIF IP pins are assigned to identical locations in the HPS IO banks. |
| Pin missing (1) | Design 1:
Design 2:
The remaining pins are either empty or used for identical HPS EMIF IP in both designs. |
In design 2, the PIN_F12 pin is used in one HPS IO bank but not in the other, causing an IO hash difference. To fix this, either move gpio[2] in design 2 to a different bank or add gpio[2] in design 1 and place it in the same pin. |
| Pin missing (2) |
Design 1:
Design2:
The remaining pins are either empty or used for identical HPS EMIF IP in both designs. |
In design 1, the PIN_H24 pin is used in one HPS IO bank but not in the other design which causes an IO hash difference. To fix this, either move gpio[1] in design 1 to a different bank or add gpio[1] in design 2 and place it in the same pin. |
| Pin swapping |
Design 1:
Design 2:
The remaining pins are either empty or used for identical HPS EMIF IP in both designs. |
The PIN_G17 and PIN_H24 are assigned to different top-level ports, which is likely to cause IO hash differences. To avoid this, assign the same top-level ports to the same pins. To fix the design, swap the gpio[1] and gpio[0] pin assignments in either design 1 or design 2. |
| Pin configuration |
Design 1:
Design 2:
The remaining pins are either empty or used for identical HPS EMIF IP in both designs. However, their configurations might differ between the two designs. |
The pin placement itself does not cause differences; however, the configuration of gpio[0] and gpio[1] must still match between designs. For more information, see IO Configuration Differences on non-HPS EMIF IPs. |
| PLL Differences | ||
| Output clock frequency in PLL IP | In both designs, the PLL IP is placed in the HPS IO bank and configured to take a 100 MHz reference clock. However, in design 1, the output clock frequency is 150 MHz, and in design 2, the output clock frequency is 100 MHz. |
The output clock frequency is configured differently between the two designs, causing an IO hash difference. To fix this, open the Platform Designer GUI and ensure the IP configurations are identical in both designs. |
| Non-HPS EMIF PLL placement | A non-HPS EMIF PLL is placed into the HPS IO bank in design 1 only. |
The IO hash mismatches because non-HPS EMIF PLLs placed in the HPS IO banks contribute to the HPS IO hash. Check the Pin Planner and Chip Planner (or Interface Planner) to ensure the same set of locations is occupied in each design. |
| Non-HPS EMIF PLL with global/non-global clock | In design 1, a non-HPS EMIF PLL inside the HPS IO bank uses a global clock. In design 2, the same PLL uses a non-global clock. |
The IO hash mismatches because the clock routing for the PLL clocks contributes to the HPS IO hash. Check the "Global & Other Fast Signals Summary" section of the compilation report. For the PLLs placed in the HPS IO banks, ensure that each of their clocks (including reference and output clocks) is either present in this table in both designs or absent from this table in both designs. |
| PLLs location swapped | The PLL1 and PLL2 are placed in an HPS IO bank in both designs. Design 1:
Design 2:
|
This likely causes IO hash differences. Ensure that the same PLLs are assigned to the same locations in each design. To adjust the design, you need to swap PLL locations in either design 1 or design 2. |
| PLL reference clock via dedicated/global clock path | A PLL is placed in an HPS IO bank with a reference clock coming from another PLL placed in a non-HPS IO bank (cascading). In design 1 the reference clock is routed via dedicated clock path while in design 2 this is routed via a global clock tree. | When the clock driving the PLL reference clock is coming from a different source, this influences the IO hash. In this example, the source location is another PLL providing a clock through PLL cascading; the same applies when the clock originates from a pin. To adjust the design, you need to look up the source of the PLL in your design RTL and ensure that it is using the same "global" setting and that it is placed in the same location in both designs. |
| PLL output clock via dedicated/global clock path | A PLL is placed in an HPS IO bank cascading its output clock to a non-HPS IO bank. In design 1 the output clock is provided via a dedicated clock path. In design 2 this is done via a global clock tree. |
When the clock driven by the PLL leaves the bank via a different path, it affects the IO hash. In this example, the source PLL drives another PLL, but the same applies when the clock drives an IO pin or other logic in another bank. To fix the design, check the destination of the PLL in your design RTL and ensure it uses the same global setting and is placed in the same location in both designs. |
| Clock Spine Differences | ||
| Non-HPS EMIF PLL clock spine | A clock driving a non-HPS EMIF PLL inside the HPS IO bank uses a different clock spine in each design. | The IO hash mismatches because the clock spine selection is part of the HPS IO bank and contributes to the HPS IO hash. Check the "Terminating Spine Index" in the "Global & Other Fast Signals Details" section of the compilation report. For any clock in this report that drives a PLL in the HPS IO bank, ensure they are set to the same value in both designs. |
| PLL clock spine index | A PLL IP is placed in the HPS IO bank, has a global reference clock, and is clocked by the clk_from_pin pin. In design 1 this clock has a spine index of 5. In design 2 this clock has a spine index of 4. | The IO hash differs because the GPIOs are clocked by clocks with different clock spines in the two designs. To fix this, you must set the clk_from_pin clock spine value to either 4 or 5 in both designs (either value is acceptable). |
| Non-HPS EMIF GPIO clock spine | A clock driving a non-HPS EMIF GPIO inside the HPS IO bank uses a different clock spine in each design. | The IO hash mismatches because the clock spine selection is part of the HPS IO bank and contributes to the HPS IO hash. Check the "Terminating Spine Index" in the "Global & Other Fast Signals Details" section of the compilation report. For any clock in this report that drives a GPIO (including DDR and SDR mode) in the HPS IO bank, they must be set to the same value in both designs. |
| DDR GPIO IP pin clock spine | The gpio[0] data pin of the GPIO IP is in DDR mode, placed in the HPS IO bank, and clocked by pll|outclk_0. In design 1, this clock has a spine index value of 5, In design 2, this clock has a spine index value of 4. | The IO hash differs because the GPIOs are clocked by clocks with different clock spines in the two designs. To fix the design, you need to set the pll|outclk_0 clock spine value to either 4 or 5 in both designs (either value is acceptable). |
| DDR GPIO IP pin clock region | The gpio[0] data pin of the GPIO IP is in DDR mode, placed in the HPS IO bank, and clocked by pll|outclk_0, which has a spine index value of 5. In design 1, the clock region area is (0, 2) to (1, 3), In design 2, the clock region area is (0, 1) to (1, 3). | Even though the clock region differs, the clock spine is the same, so this difference does not affect the HPS IO hash. |
| Register packed GPIO pin clock spine | The gpio[0] data pin in the HPS IO bank is not driven by a GPIO IP, but has a register-packed upstream register clocked by pll|outclk_0. In design 1, this clock has a spine index value of 5, In design 2, this clock has a spine index value of 4. | The IO hash differs because the packed registers are clocked by clocks with different spines in the two designs. To fix this, set the clk_from_pin clock spine value to either 4 or 5 in both designs (either value is acceptable). |
| Register Packing Differences | ||
| Output GPIO pin from register register/not-register packed | The gpio[0] output pin in the HPS IO bank has an upstream register. In design 1, this register is packed. In design 2, this register is not packed. | The IO hash differs. To fix this, ensure that either both registers are packed or neither register is packed. |
| Input GPIO pin from register register/not-register packed | The gpio[0] input pin in the HPS IO bank has a downstream register. In design 1, this register is packed. In design 2, this register is not. | The IO hash differs. To fix this, ensure that either both registers are packed or neither register is packed. |