Hard Processor System Booting User Guide: Agilex™ 5 SoCs

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ID 813762
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. HPS Boot Flows 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 5 SoC FPGA Boot Flow 8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs
1. Introduction x
1.1. Glossary 1.2. Agilex™ 5 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration First - Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 3.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration 4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options 4.2.3. Generation of Debug HPS FSBL from Hardware Design Build
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices x
4.11.1. Data Retention Mechanism Flow 4.11.2. Setting to Enable the Data Retention Mechanism 4.11.3. Preserving Data in SDRAM Across Reset Examples
5. HPS Boot Flows x
5.1. U-Boot ATF Linux* Boot 5.2. ATF Linux Boot 5.3. ATF Zephyr* Boot
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux* 6.3. FPGA Partial Reconfiguration from Linux* 6.4. Hardware Project Compatibility in HPS Boot First Mode
6.4. Hardware Project Compatibility in HPS Boot First Mode x
6.4.1. HPS IO Hash Compatibility 6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s)
6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s) x
6.4.2.1. IO Configuration Differences on non-HPS EMIF IPs 6.4.2.2. Pin Location Differences 6.4.2.3. PLL Differences 6.4.2.4. Clock Spine Differences 6.4.2.5. HPS IO Hash Mismatch Troubleshooting Examples for HPS EMIF IOs
6.4.2.4. Clock Spine Differences x
6.4.2.4.1. Agilex™ 5-Specific Clock Spine Differences 6.4.2.4.2. Register Packing Differences
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA) Edition
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs

6.4.1. HPS IO Hash Compatibility

You can ensure compatibility between bitstream sections in different designs primarily through the HPS IO hash. The Quartus® Prime Assembler calculates the HPS IO hash, producing a 64-character hexadecimal string using a cryptographic algorithm. This algorithm operates over the configuration data of specific IO banks, which are described later in this document.

If an HPS IO hash is incompatible, you must adjust one of the two designs. The next figure shows the error message that appears when U-Boot requests the second phase FPGA configuration and finds an incompatible HPS IO hash between the phase 1 and phase 2 FPGA designs.

Figure 40. Error Message for Incompatible HPS IO Hash between Phase 1 and Phase 2 FPGA Designs

Use the quartus_pfg tool to manually retrieve the HPS IO hash for phase 1 and phase 2 FPGA designs, as shown in the following table. The table shows the command with the necessary parameters and an example of the output.

Table 17.  Manually Retrieve the HPS IO Hash for Phase 1 and Phase 2 FPGA Designs
Design Command
Phase 1 quartus_pfg -i <jic file>
Phase 2 quartus_pfg -i <core.rbf>
Note: The above example shows an Agilex™ 7device, but the same methodology to extract the HPS IO Hash also applies to Agilex™ 5 devices.

You can also use the Configuration Debugger tool in Quartus® Prime Pro Edition to retrieve the HPS IO hash. Use the .jic file as the input for Phase 1 and the .core.rbf file as the input for Phase 2. The following figure shows an example of this process.

Figure 41. Configuration Debugger Tool
Note: The above example shows an Agilex™ 7device, but the same methodology to extract the HPS IO Hash also applies to Agilex™ 5 devices.
For the HPS to boot, it uses one of the following IPs to connect with the main memory, and device IO banks are needed to interface with the memory. In all cases, device IO banks are needed to interface with memory:
  • HPS EMIF
  • EMIF + NoC-only supported by Agilex™ 7 M-Series

The key point about the HPS IO hash is that the full contents of the IO banks contribute to it. For example, if the IO banks are used for the HPS EMIF IP, all placement, routing, and parameter settings within those banks must be identical between the two designs being compared. This includes any non-HPS-EMIF-related hard IPs, such as PLL and GPIO, that are placed in the same bank as the HPS EMIF IP.

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