Hard Processor System Booting User Guide: Agilex™ 5 SoCs

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ID 813762
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. HPS Boot Flows 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 5 SoC FPGA Boot Flow 8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs
1. Introduction x
1.1. Glossary 1.2. Agilex™ 5 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration First - Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 3.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration 4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options 4.2.3. Generation of Debug HPS FSBL from Hardware Design Build
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices x
4.11.1. Data Retention Mechanism Flow 4.11.2. Setting to Enable the Data Retention Mechanism 4.11.3. Preserving Data in SDRAM Across Reset Examples
5. HPS Boot Flows x
5.1. U-Boot ATF Linux* Boot 5.2. ATF Linux Boot 5.3. ATF Zephyr* Boot
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux* 6.3. FPGA Partial Reconfiguration from Linux* 6.4. Hardware Project Compatibility in HPS Boot First Mode
6.4. Hardware Project Compatibility in HPS Boot First Mode x
6.4.1. HPS IO Hash Compatibility 6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s)
6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s) x
6.4.2.1. IO Configuration Differences on non-HPS EMIF IPs 6.4.2.2. Pin Location Differences 6.4.2.3. PLL Differences 6.4.2.4. Clock Spine Differences 6.4.2.5. HPS IO Hash Mismatch Troubleshooting Examples for HPS EMIF IOs
6.4.2.4. Clock Spine Differences x
6.4.2.4.1. Agilex™ 5-Specific Clock Spine Differences 6.4.2.4.2. Register Packing Differences
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA) Edition
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs

4.11.1. Data Retention Mechanism Flow

The following diagram shows the data retention flow process.

Figure 34. Data Retention Mechanism Flow

The following steps explain the flow in the diagram above:

  1. After the initial power-on, early in the SDRAM initialization, the FSBL sets the boot_scratch_por0[0] bit at HPS address 0x10D12258 to indicate the initialization has started but is not yet complete.
    boot_scratch_por0[0] Description (HPS Address 0x10D12258)
    0 DDR Memory was initialized successfully.
    1 DDR Memory initialization did not complete.
  2. The FSBL executes the SDRAM initialization stages, which include configuring IO96B and MPFE, performing DDR calibration, initializing the IOSSM mailbox, and obtaining SDRAM parameters. These stages can either succeed or fail. If a failure occurs, the boot_scratch_por0[0] remains set.
  3. The FSBL determines if a full initialization is needed by evaluating the following conditions:
    Condition How read? Notes

    ECC enabled in SDRAM.

    ecc_status

    		Read from memory controller using the IOSSM mailbox. Enabled from hardware Quartus project.

    Reset type.

    reset_type

    		Read from boot_scratch_cold3[31:29]

    Set by SDM during HPS bring up.

    POR_RESET = 0

    WARM_RESET =1

    COLD_RESET = 2

    NCONFIG = 3

    JTAG_CONFIG = 4

    RSU_RECONFIG =5

    Double bit error (DBE) in SDRAM

    DDR_ECC_DBE

    		Read from boot_scratch_cold3[1]

    Set by SDM during SDRAM bring up.

    1: DBE found in SDRAM

    0: No DBE found in SDRAM

    Double Bit Error (DBE) in OCRAM.

    OCRAM_DBE

    		Read from boot_scratch_cold3[0]

    Set by SDM during OCRAM bring up

    1: DBE found in OCRAM

    0: No DBE found in OCRAM

    Previous SDRAM initialization failed.

    ddr_init_n

    		Read from boot_scratch_por0[0]

    Set and clear by FSBL at the start and end of SDRAM initialization. Backed up by SDM during a WARM or COLD reset.

    See previous table for bit value description. You can also manually set this bit to request a full DDR initialization (if the other conditions are also valid for this purpose).

    To perform the full SDRAM initialization, you must enable ECC in SDRAM (ecc_status = 1) along with any of the following scenarios:

    • Previous initialization did not complete successfully (ddr_init_n = 1).
    • DBE Errors in OCRAM were found (OCRAM_DBE = 1).
    • DBE Errors in SDRAM were found (DDR_ECC_DBE = 1).
    • The reset type is different from WARM and COLD reset (reset_type ≠ 1 and reset_type ≠ 2).

    Based on these criteria, after a POR, a full initialization is expected if ECC is enabled in SDRAM. During a full initialization, BIST runs over the SDRAM, resulting in the loss of any existing data.

  4. Following the flow in the diagram, after SDRAM initialization completes, the HPS can begin using the SDRAM to read and write data.
    • Based on overall system requirements, you can flush the caches before a warm or cold reset occurs, when possible.
    • Based on overall system requirements, you can set the boot_scratch_por[0] bit to force a full SDRAM initialization (if ECC is enabled in SDRAM) during the next warm or cold reset.
  5. The warm or cold reset is requested.
  6. The reset is processed by the SDM firmware analyzing the type of reset requested and the state of previous initialization. The following table describes what the SDM does during this stage.
    Table 16.  SDM Reset Types and States
    Condition HPS is reset? HNOC & IO96B are reset? FPGA fabric is wiped? SDRAM preserved? Notes
    jtag config or nConfig Yes Yes Yes No Reset is reported as JTAG_CONFIG or NCONFIG.
    HPS Cold reset Yes No No Yes 1 Reset state is reported as Cold.
    HPS Warm reset Yes No No Yes1 Reset state is reported as Warm.
    HPS Cold reset to recover from DDR initialization failure (ddr_init_n = 1) Yes Yes Yes No1 POR reset is asserted affecting HNOC and IO96B. Reset state is reported as Cold. Full memory initialization is performed.
    HPS Warm reset to recover from DDR initialization failure (ddr_init_n = 1) Yes yes Yes No1 This is converted into a cold reset (see HPS Cold reset to recover from DDR initialization failure) in previous row). Full memory initialization is performed.
    HPS Reconfig FPGA (HPS Boot First) No No Yes Yes No reset is observed.
    HPS Reconfig FPGA (FPGA Boot first) Unsupported
    HPS Cold/Warm reset to recover from DDR DBE with ECC enable. Yes No No No1 Reset state is reported as Cold or Warm reset depending on which was requested. DDR memory need to be recalibrated and full memory initialization performed.
    HPS Cold/Warm reset to recover from OCRAM DBE with ECC enable. Yes No No No1 Reset state is reported as Cold or Warm reset depending on which was requested. Full memory initialization is performed.

    In all the reset scenarios listed in the table, the SDM also backs up and restores the boot_scratch_por0[0] register which includes the SDRAM initialization status before the reset, and updates boot_scratch_cold3[31:29] with the identified reset type. Additionally, for scenarios 8 and 9, the SDM updates the DBE status of SDRAM and OCRAM during their initialization before releasing the HPS from reset.

  7. After an HPS reboot, during SDRAM initialization, the FSBL reads the boot_scratch_por[0] bit and keeps it internally for later analysis.
  8. The FSBL then executes the main SDRAM initialization stages.
  9. If the main SDRAM initialization stages succeed, the FSBL determines if a full initialization is required, as previously described. The FSBL then checks the internally saved value of boot_scratch_por0[0] to verify if the previous SDRAM initialization was completed successfully. If a full initialization is required, the FSBL performs BIST, which results in the loss of data in SDRAM. If a full initialization is not required, the data in SDRAM is preserved.

The following diagram shows the SDRAM initialization flow in the FSBL.

Figure 35. SDRAM Initialization Flow
1 Result assuming SDRAM ECC is enabled (ecc_status = 1) and the conditions in the Condition column are the only ones present. For other conditions, check if data in SDRAM is preserved evaluating if full DDR initialization is performed as indicated previously.
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