Hard Processor System Booting User Guide: Agilex™ 5 SoCs

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ID 813762
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. HPS Boot Flows 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 5 SoC FPGA Boot Flow 8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs
1. Introduction x
1.1. Glossary 1.2. Agilex™ 5 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration First - Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 3.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration 4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options 4.2.3. Generation of Debug HPS FSBL from Hardware Design Build
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices x
4.11.1. Data Retention Mechanism Flow 4.11.2. Setting to Enable the Data Retention Mechanism 4.11.3. Preserving Data in SDRAM Across Reset Examples
5. HPS Boot Flows x
5.1. U-Boot ATF Linux* Boot 5.2. ATF Linux Boot 5.3. ATF Zephyr* Boot
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux* 6.3. FPGA Partial Reconfiguration from Linux* 6.4. Hardware Project Compatibility in HPS Boot First Mode
6.4. Hardware Project Compatibility in HPS Boot First Mode x
6.4.1. HPS IO Hash Compatibility 6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s)
6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s) x
6.4.2.1. IO Configuration Differences on non-HPS EMIF IPs 6.4.2.2. Pin Location Differences 6.4.2.3. PLL Differences 6.4.2.4. Clock Spine Differences 6.4.2.5. HPS IO Hash Mismatch Troubleshooting Examples for HPS EMIF IOs
6.4.2.4. Clock Spine Differences x
6.4.2.4.1. Agilex™ 5-Specific Clock Spine Differences 6.4.2.4.2. Register Packing Differences
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA) Edition
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs

7.1. Reset

Table 20.  Reset Effects on Booting and Configuration
Reset Type Initiated By Details

Power-on Reset

An external event
  • The entire HPS and FPGA are reset.
  • When the device is released from POR, SDM begins initialization. A POR is the only way initialization can begin.
  • POR is the only way to recover from a tamper event.

nCONFIG Reset

nCONFIG pin

An SoC device-wide reset input that cold resets the HPS and reconfigures the FPGA.

Cold Reset
  • SDM
  • HPS_COLD_nRESET pin
  • Watchdog Timeout Event (calls SDM)
  • FPGA mailbox request to SDM
  • All of HPS, except the HPS I/O, Clock Manager, Reset Manager, and the TAP controller, are reset.
  • An HPS cold reset does not impact the FPGA core and FPGA I/O (the device is not reconfigured).
  • The SDM reloads the FSBL into on-chip RAM.
  • When the HPS_COLD_nRESET pin asserts, the SDM begins the reset sequence.
  • Data present in SDRAM survives to this reset under normal conditions (see Preserving SDRAM Content across HPS Resets for Devices for any other conditions).

Cold and Trigger Remote Update Reset

Watchdog Timeout Event (calls SDM)
  • SDM requests reset manager to assert or de-assert cold reset.
  • When the HPS_COLD_nRESET pin asserts, the SDM begins the reset sequence.
  • The SDM loads the FSBL from the next bitstream or factory bitstream into on-chip RAM.
  • The FPGA is first erased and then loaded with an image from the next bitstream or factory bitstream. There must always be a factory image present.

Warm Reset
  • FSBL or any software that makes a warm reset request through the EL3 register2 software write to the RMR_EL3 register to trigger a warm reset to the CPUs. You can still use debug tools after a warm reset because it does not reset the debug modules. The SDM does not reload the FSBL on a warm reset. You must ensure that your FSBL can support reentry, or that your on-chip RAM contains the FSBL or minimum required to boot the system.
  • Watchdog Timeout Event (calls SDM)
  • Before you can write to the RMR_EL3 register, CPU0 must ensure that the other CPUs are in WFI mode. Immediately after the RMR_EL3 register is written, the WFI instruction must be executed.
  • All of the HPS, except debug, MPU debug, and the boot scratch registers in the System Manager are reset.
  • A warm reset does not reload the FSBL into the HPS. The FSBL remains in the on-chip RAM during a warm reset.
  • Warm reset of the HPS does not impact the FPGA core and I/O (the device is not reconfigured).
  • In the case of a single configuration and boot source, warm reset returns flash control from HPS to SDM.
  • Data present in SDRAM survives to this reset under normal conditions (see Preserving SDRAM Content across HPS Resets for Devices for any other conditions).

Software Reset

A software write to the Reset Manager
  • A software reset of a CPU does not affect SDM functionality.

Watchdog Reset

Timeout from a user configurable watchdog timer register.
  • Each CPU has a dedicated watchdog timer.
  • L4 Watchdog Timer 0 is configured during HPS initialization.
  • Use the Quartus® Prime Pro Edition to configure the watchdog reset for an HPS cold, HPS warm, or HPS cold and trigger remote update reset. See other entries in this table for details on each reset type.

Debug Reset

JTAG SRST pin
  • To control reset, you must connect the HPS_COLD_nRESET pin to the JTAG SRST pin.
  • A debug reset initiates a cold reset.

JTAG Reset

JTAG SRST pin
  • JTAG can reset the entire device regardless of the MSEL[2:0] settings and reload a new configuration or test through JTAG.

Section Content
HPS Reset Pin
L4 Watchdog Timer 0

Related Information
Level Two Title