Hard Processor System Booting User Guide: Agilex™ 5 SoCs

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ID 813762
Date 12/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. FPGA Configuration First Mode 3. HPS Boot First Mode 4. Creating the Configuration Files 5. HPS Boot Flows 6. Configuring the FPGA Fabric from HPS Software 7. Debugging the Agilex™ 5 SoC FPGA Boot Flow 8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs
1. Introduction x
1.1. Glossary 1.2. Agilex™ 5 SoC FPGA Boot Overview
2. FPGA Configuration First Mode x
2.1. Boot Flow Overview for FPGA Configuration First Mode 2.2. System Layout for FPGA Configuration First Mode
2.1. Boot Flow Overview for FPGA Configuration First Mode x
2.1.1. Power-On Reset (POR) 2.1.2. Secure Device Manager 2.1.3. First-Stage Bootloader 2.1.4. Second-Stage Bootloader 2.1.5. Operating System 2.1.6. Application
2.2. System Layout for FPGA Configuration First Mode x
2.2.1. External Configuration Host Only 2.2.2. External Configuration Host with HPS Flash 2.2.3. Single SDM Flash 2.2.4. FPGA Configuration First - Dual Flash System
3. HPS Boot First Mode x
3.1. Boot Flow Overview 3.2. System Layout for HPS Boot First Mode
3.1. Boot Flow Overview x
3.1.1. Power-On Reset (POR) 3.1.2. Secure Device Manager 3.1.3. First-Stage Bootloader 3.1.4. Second-Stage Bootloader 3.1.5. Operating System 3.1.6. Application
3.2. System Layout for HPS Boot First Mode x
3.2.1. External Configuration Host Only 3.2.2. External Configuration Host with HPS Flash 3.2.3. Single SDM Flash 3.2.4. HPS Boot First - Dual Flash System
4. Creating the Configuration Files x
4.1. Overview 4.2. Quartus® Prime Hardware Project Compilation 4.3. Bootloader Software Compilation 4.4. Programming File Generator 4.5. Configuration over JTAG 4.6. Configuration from QSPI 4.7. Configuration over AVST 4.8. Configuration via Protocol 4.9. Remote System Update 4.10. Partial Reconfiguration 4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices
4.2. Quartus® Prime Hardware Project Compilation x
4.2.1. Device and Pin Options 4.2.2. Platform Designer Options 4.2.3. Generation of Debug HPS FSBL from Hardware Design Build
4.5. Configuration over JTAG x
4.5.1. FPGA Configuration First 4.5.2. HPS Boots First
4.6. Configuration from QSPI x
4.6.1. Supported QSPI Devices 4.6.2. FPGA Configuration First 4.6.3. HPS Boot First
4.6.2. FPGA Configuration First x
4.6.2.1. Creating Configuration Files from Command Line 4.6.2.2. Creating Configuration Files Using Graphical Interface
4.6.3. HPS Boot First x
4.6.3.1. Creating Configuration Files from Command Line 4.6.3.2. Creating Configuration Files Using Graphical Interface
4.7. Configuration over AVST x
4.7.1. FPGA Configuration First 4.7.2. HPS Boot First
4.7.1. FPGA Configuration First x
4.7.1.1. Creating Configuration Files from Command Line 4.7.1.2. Creating Configuration Files Using Graphical Interface
4.7.2. HPS Boot First x
4.7.2.1. Creating Configuration Files from Command Line 4.7.2.2. Creating Configuration Files Using Graphical Interface
4.8. Configuration via Protocol x
4.8.1. Creating Configuration Files from Command Line 4.8.2. Creating Configuration Files Using Graphical Interface
4.11. Preserving SDRAM Content across HPS Resets for Agilex™ 5 Devices x
4.11.1. Data Retention Mechanism Flow 4.11.2. Setting to Enable the Data Retention Mechanism 4.11.3. Preserving Data in SDRAM Across Reset Examples
5. HPS Boot Flows x
5.1. U-Boot ATF Linux* Boot 5.2. ATF Linux Boot 5.3. ATF Zephyr* Boot
6. Configuring the FPGA Fabric from HPS Software x
6.1. Configuring the FPGA Fabric from U-Boot 6.2. Configuring the FPGA Fabric from Linux* 6.3. FPGA Partial Reconfiguration from Linux* 6.4. Hardware Project Compatibility in HPS Boot First Mode
6.4. Hardware Project Compatibility in HPS Boot First Mode x
6.4.1. HPS IO Hash Compatibility 6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s)
6.4.2. HPS IO Hash Handling as related to the HPS EMIF IO Bank(s) x
6.4.2.1. IO Configuration Differences on non-HPS EMIF IPs 6.4.2.2. Pin Location Differences 6.4.2.3. PLL Differences 6.4.2.4. Clock Spine Differences 6.4.2.5. HPS IO Hash Mismatch Troubleshooting Examples for HPS EMIF IOs
6.4.2.4. Clock Spine Differences x
6.4.2.4.1. Agilex™ 5-Specific Clock Spine Differences 6.4.2.4.2. Register Packing Differences
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow x
7.1. Reset 7.2. Debugging the HPS Bootloader Using the Arm* Development Studio for Intel® SoC FPGA (Arm* DS for Intel® SoC FPGA) Edition
7.1. Reset x
7.1.1. HPS Reset Pin 7.1.2. L4 Watchdog Timer 0
1. Introduction
2. FPGA Configuration First Mode
3. HPS Boot First Mode
4. Creating the Configuration Files
5. HPS Boot Flows
6. Configuring the FPGA Fabric from HPS Software
7. Debugging the Agilex™ 5 SoC FPGA Boot Flow
8. Document Revision History for the Hard Processor System Booting User Guide: Agilex™ 5 SoCs

4.11.3. Preserving Data in SDRAM Across Reset Examples

The following example demonstrates the SDRAM Data Retention mechanism during a Warm reset using the U-Boot shell. In this example, data is written to the memory address specified by the loadaddr environment variable. A Warm reset is then initiated using the reset command and setting the reset environment variable to warm. In this case, a cache flush is not needed, as it is handled by U-Boot during the execution of the socfpga_sysreset_request() function in drivers/sysreset/sysreset_socfpga_agilex5.c file. After the reboot, you can see that the reset state printed by U-Boot SPL corresponds to a Warm reset triggered by SDM (with ATF sending a request through the SDM mailbox). Once back in the U-Boot shell, the same memory locations are read to verify that the data has survived the reset. 

# Write some data in a SDRAM memory location
SOCFPGA_AGILEX5 # mw ${loadaddr} 0xcafecafe 0x10
SOCFPGA_AGILEX5 # md ${loadaddr} 10
82000000: cafecafe cafecafe cafecafe cafecafe  ................
82000010: cafecafe cafecafe cafecafe cafecafe  ................
82000020: cafecafe cafecafe cafecafe cafecafe  ................
82000030: cafecafe cafecafe cafecafe cafecafe  ................
# Triger a Warm Reset
SOCFPGA_AGILEX5 # setenv reset warm
SOCFPGA_AGILEX5 # reset
resetting ...
Do warm reset now...

<reboot occurs here>

U-Boot SPL 2023.10-31805-g69d5338be0-dirty (May 22 2024 - 14:26:16 -0500)
Reset state: Warm [from SDM]
:
Hit any key to stop autoboot:  0 
# Reading back the preserved data 
SOCFPGA_AGILEX5 # md ${loadaddr} 10
82000000: cafecafe cafecafe cafecafe cafecafe  ................
82000010: cafecafe cafecafe cafecafe cafecafe  ................
82000020: cafecafe cafecafe cafecafe cafecafe  ................
82000030: cafecafe cafecafe cafecafe cafecafe  ................

The following code snippet demonstrates the same example, but this time issuing a cold reset. Here, the reset command is called without defining any value for the reset environment variable, resulting in a cold reset. In this scenario, the data written to SDRAM is automatically flushed from the cache to SDRAM as part of the handling of the PSCI_SYSTEM_RESET command by the SMC handler in the Arm Trusted Firmware. After the reboot, the reset state printed by U-Boot SPL indicates that a cold reset occurred. Once back in the U-Boot shell, the same memory locations are read to verify that the data has also survived this reset. 

# Write some data in a SDRAM memory location
SOCFPGA_AGILEX5 # mw ${loadaddr} 0xcafecafe 0x10
SOCFPGA_AGILEX5 # md ${loadaddr} 0x10
82000000: cafecafe cafecafe cafecafe cafecafe  ................
82000010: cafecafe cafecafe cafecafe cafecafe  ................
82000020: cafecafe cafecafe cafecafe cafecafe  ................
82000030: cafecafe cafecafe cafecafe cafecafe  ................
# Triger a Cold reset
SOCFPGA_AGILEX5 # reset
resetting ...
Issuing cold reset REBOOT_HPS

<reboot occurs here>

U-Boot SPL 2023.10-31805-g69d5338be0-dirty (May 22 2024 - 14:26:16 -0500)
Reset state: Cold
:
Hit any key to stop autoboot:  0 
# Reading back the preserved data 
SOCFPGA_AGILEX5 # md ${loadaddr} 0x10
82000000: cafecafe cafecafe cafecafe cafecafe  ................
82000010: cafecafe cafecafe cafecafe cafecafe  ................
82000020: cafecafe cafecafe cafecafe cafecafe  ................
82000030: cafecafe cafecafe cafecafe cafecafe  ................

In the Agilex™ 5 device, the flow to process the reset command to trigger a warm or cold reset issued from U-Boot, and also the reboot command from Linux, is done requesting this reset to the SDM though the SMC handler in the Arm Trusted Firmware (ATF). The SMC handler process the reset request from U-Boot and Linux, performs some operations like flushing the cache memories (under certain conditions), and finally forwards the reset request to SDM using the REBOOT_HPS command through the SDM mailbox. This flow is shown in the following figure.

In the Agilex™ 5 device, the process for handling the reset command to trigger a warm or cold reset from U-Boot, as well as the reboot command from Linux, involves requesting the reset from the SDM through the SMC handler in the Arm Trusted Firmware (ATF). The SMC handler processes the reset request from U-Boot and Linux, performs operations such as flushing the cache memories (under certain conditions), and finally forwards the reset request to the SDM using the REBOOT_HPS command through the SDM mailbox. This flow is illustrated in the following figure.

Figure 36. Reset Command Triggers a Warm or Cold Reset Flow
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