Hard Processor System Booting User Guide: Agilex™ 5 SoCs
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Ixiasoft
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Ixiasoft
4.6.3.1. Creating Configuration Files from Command Line
quartus_pfg -c design.sof design.jic design.rpd design.map \ -o hps_path=fsbl.hex \ -o device=MT25QU128 \ -o flash_loader=A5ED065BB32AR0 \ -o mode=ASX4 \ -o hps=on \ -o bitswap=on
- Input Files:
- design.sof
- fsbl.hex
- Output Files:
- design.jic
- design.core.rbf
- design.rpd (optional)
- design.map (optional)
Parameter | Description |
---|---|
hps_path | Location of HPS FSBL file in hex format |
device | Target QSPI device. Use a device listed in Supported QSPI Devices or use the graphical interface to determine available options. |
flash_loader | The helper image to be used for writing JIC to QSPI Flash. It is typically an alphanumeric prefix of your FPGA part number. You may use the graphical interface mode to determine available options |
mode | AS x4 for QSPI |
bitswap | Set to "on" to create RPD with plain binary format, usable by 3rd party tools. |
hps | Set to "on" to enable HPS boot first mode, omit for FPGA configuration first mode |