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4.6.1. Launching and Setting Up the Fault Injection Debugger
4.6.2. Configuring Your Device using a Software Object File (.sof)
4.6.3. Constraining Regions for Fault Injection
4.6.4. Injecting Errors to Predefined Safe Locations
4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types
4.6.6. Injecting Errors to Random Locations
4.6.7. Injecting Errors to Specific Locations
4.6.8. Injecting Double Adjacent Errors
4.6.9. Injecting SDM ECC Errors
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2.1. CRAM Error Detection and Correction
Agilex™ 5 devices feature on-chip EDC circuitry to detect soft errors. If you enable the internal scrubbing feature, the Agilex™ 5 FPGA corrects an error caused by an SEU event if it is correctable.
Error Type | Detection | Correction |
---|---|---|
Single bit error | Yes | Yes |
Double adjacent errors | Yes | Yes |
Multiple bits error | Yes | — |
The EDC operation runs simultaneously for all sectors in Agilex™ 5 devices.
For more information about implementing ECC with the embedded memory Intel FPGA IP cores, refer to the Agilex™ 5 Embedded Memory User Guide.