SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

ID 813649
Date 9/20/2024
Public
Document Table of Contents

2.1. CRAM Error Detection and Correction

Agilex™ 5 devices feature on-chip EDC circuitry to detect soft errors. If you enable the internal scrubbing feature, the Agilex™ 5 FPGA corrects an error caused by an SEU event if it is correctable.
Table 3.  Detection and Correction of Error Types
Error Type Detection Correction
Single bit error Yes Yes
Double adjacent errors Yes Yes
Multiple bits error Yes

The EDC operation runs simultaneously for all sectors in Agilex™ 5 devices.

For more information about implementing ECC with the embedded memory Intel FPGA IP cores, refer to the Agilex™ 5 Embedded Memory User Guide.