SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813649
Date 9/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 SEU Mitigation Overview 2. Agilex™ 5 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Agilex™ 5 SEU Mitigation Implementation Guides 5. IP and Software References 6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Agilex™ 5 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets 2.7. Retrieving SEU Statistics using Mailbox Command
2.2. Error Message Queue x
2.2.1. SEU_ERROR Pin Behavior 2.2.2. Retrieving the Error Message Queue Contents Through Mailbox Command 2.2.3. Retrieving the Error Message Queue Content Using the HPS SDM Mailbox 2.2.4. Error Message Queue Bit Description
2.3. Scrubbing x
2.3.1. Internal Scrubbing 2.3.2. External Scrubbing
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Agilex™ 5 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Performing External Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Predefined Safe Locations 4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types 4.6.6. Injecting Errors to Random Locations 4.6.7. Injecting Errors to Specific Locations 4.6.8. Injecting Double Adjacent Errors 4.6.9. Injecting SDM ECC Errors
4.6.4. Injecting Errors to Predefined Safe Locations x
4.6.4.1. Listing the Predefined Safe Locations: Command-Line Interface 4.6.4.2. Injecting Errors to Predefined Safe Locations: Command-Line Interface 4.6.4.3. Injecting Errors to Predefined Safe Locations: GUI with Tcl Console 4.6.4.4. Injecting Error to Predefined Safe Locations: Mailbox Command
4.6.8. Injecting Double Adjacent Errors x
4.6.8.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.8.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.6.9. Injecting SDM ECC Errors x
4.6.9.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.9.2. Injecting SDM ECC Errors: GUI with Tcl Console 4.6.9.3. Injecting SDM ECC Errors: Fault Injection Debugger 4.6.9.4. Injecting SDM ECC Errors: Mailbox Command
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection Intel® FPGA IP Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 5 SEU Mitigation Implementation Guides
5. IP and Software References
6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Quartus® Prime Version Changes
2024.09.20 24.1
  • Removed information about triple modular redundancy area from Table: SEU Mitigation Areas and Approaches for Agilex™ 5 Devices.
  • Updated the M20K features in Table: ECC for M20K Blocks.
  • Updated Secure Device Manager ECC and SmartVID.
  • Updated Figure: Configuration Debugger Response to read_seu_error Mailbox Command (0x3C).
  • Updated Retrieving SEU Statistics using Mailbox Command.
  • Updated Injecting Errors to Predefined Safe Locations: GUI with Tcl Console.
  • Updated Injecting Error to Predefined Safe Locations: Mailbox Command.
  • Added new figures:
    • Figure: Setting the SEU_ERROR Pin
    • Figure: Fault Injection Debugger Window
    • Figure: Software Object File Configuration Using Fault Injection Debugger Tool
    • Figure: Example of Listed Predefined Safe Locations at Sector 3, 4, 5, 10, 11, 12, 19, 20, and 21
    • Figure: Single-Bit Error Injection at Sector 3 Using Command Line quartus_fid
    • Figure: Single-Bit Error Injection at Sector 3 Using Tcl Console
  • Updated Secure Device Manager ECC and SmartVID Errors Detection.
  • Updated the following tables:
    • Table: SDM and Subsystem ECC Error Message Bits Description
    • Table: SmartVID Error Message Bits Description
  • Made editorial edits throughout the document.
2024.04.01 24.1 Initial release.
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