SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813649
Date 9/20/2024
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Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 SEU Mitigation Overview 2. Agilex™ 5 CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Agilex™ 5 SEU Mitigation Implementation Guides 5. IP and Software References 6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Agilex™ 5 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets 2.7. Retrieving SEU Statistics using Mailbox Command
2.2. Error Message Queue x
2.2.1. SEU_ERROR Pin Behavior 2.2.2. Retrieving the Error Message Queue Contents Through Mailbox Command 2.2.3. Retrieving the Error Message Queue Content Using the HPS SDM Mailbox 2.2.4. Error Message Queue Bit Description
2.3. Scrubbing x
2.3.1. Internal Scrubbing 2.3.2. External Scrubbing
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Agilex™ 5 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Performing External Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Predefined Safe Locations 4.6.5. Blowing Fuse Bit to Enable Injecting All Error Types 4.6.6. Injecting Errors to Random Locations 4.6.7. Injecting Errors to Specific Locations 4.6.8. Injecting Double Adjacent Errors 4.6.9. Injecting SDM ECC Errors
4.6.4. Injecting Errors to Predefined Safe Locations x
4.6.4.1. Listing the Predefined Safe Locations: Command-Line Interface 4.6.4.2. Injecting Errors to Predefined Safe Locations: Command-Line Interface 4.6.4.3. Injecting Errors to Predefined Safe Locations: GUI with Tcl Console 4.6.4.4. Injecting Error to Predefined Safe Locations: Mailbox Command
4.6.8. Injecting Double Adjacent Errors x
4.6.8.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.8.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.6.9. Injecting SDM ECC Errors x
4.6.9.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.9.2. Injecting SDM ECC Errors: GUI with Tcl Console 4.6.9.3. Injecting SDM ECC Errors: Fault Injection Debugger 4.6.9.4. Injecting SDM ECC Errors: Mailbox Command
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection Intel® FPGA IP Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Agilex™ 5 SEU Mitigation Implementation Guides
5. IP and Software References
6. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

3.1. SDM ECC Error Message Bits

The SDM ECC error message bits store the error message when the Agilex™ 5 device detects an SDM ECC error.

The SDM ECC error message contains information about the sector address and the type of error. You can retrieve the contents of the error message from the generic_sdm_data_out signal of the Advanced SEU Detection Intel® FPGA IP.

Table 7.  SDM and Subsystem ECC Error Message Bits Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in generic_sdm_data_out signal)

32 31:24 Reserved
23:16 Address of sector with error
15:8 Reserved
7:4 Error type:
  • 0000—SEU error
  • 0001—SDM and subsystem ECC error
  • 0010—miscellaneous CNT error 3
  • 0011—SmartVID error
  • 0100—miscellaneous SDM error
  • 0101—External Memory Interface
  • Remaining values—reserved
3:0 Reserved

Error data

(Least significant 32-bit word in generic_sdm_data_out signal)

32 31:29

SDM and Subsystem ECC error type:

  • 001—single bit error
  • 010—double bits error
  • 101—correctable single bit error in the transceiver
  • 110—uncorrectable multiple bits error in the transceiver
  • 111—other error classes
  • Remaining values—reserved
28 Correction status:
  • 0—not corrected
  • 1—corrected
27:12 Reserved
11:0

Specific SDM and Subsystem ECC error types 001 and 010 details: RAM_ID

Specific SDM and Subsystem ECC error type 101 details:
  • 0x02A—CRE_SERDES_ECC_CODE_ONEBIT
  • 0x02B—CRE_SERDES_ECC_DATA_ONEBIT
  • 0x02C—CRE_SERDES_ECC_CODE_ONEBIT
  • 0x02D—CRE_SERDES_ECC_DATA_ONEBIT
  • 0x02E—CRE_RSFEC_ECC_ONEBIT
Specific SDM and Subsystem ECC error type 110 details:
  • 0x010—CRE_SERDES_TWOBIT_ECC_CODE
  • 0x011—CRE_SERDES_TWOBIT_ECC_DATA
  • 0x012—CRE_SPICO_TWOBIT_ECC_CODE
  • 0x013—CRE_SPICO_TWOBIT_ECC_DATA
  • 0x014—CRE_RSFEC_ECC_TWOBIT

Specific SDM and subsystem ECC error type 111 details: 0x2F—CRE_REFCLK_FAIL

Note: When an SDM and Subsystem ECC error occurs, refer to the error data at bit [31:29] for the error type and bit [11:0] for the respective error type details and perform the necessary action accordingly.
Table 8.  SDM Miscellaneous Error Message Bits Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in generic_sdm_data_out signal)

32 31:24 Reserved
23:16 Address of sector with error
15:8 Reserved
7:4 Error Type:
  • 0000—SEU error
  • 0001—SDM and subsystem ECC Error
  • 0010—miscellaneous CNT error3
  • 0011—SmartVID error
  • 0100—miscellaneous SDM error
  • 0101—External Memory Interface
  • Remaining values—reserved
3:0 Reserved

Error data

(Least significant 32-bit word in generic_sdm_data_out signal)

32 31:29 SDM ECC error type:
  • 000—General error
  • 001—Single core TMR event
  • 111—WDT expiry event
  • Remaining values—reserved
28 Correction Status:
  • 0—not corrected
27:12 Reserved
11:0 Specific miscellaneous SDM error type 000 details:
  • 12'd16—general WDT error
  • 12'd17—nConfig WDT error
For other miscellaneous SDM error type:
  • Remaining values—reserved
Note: When an SDM Miscellaneous error occurs, refer to the error data at bit [31:29] for the error type and error data bit [11:0] for the respective error type details and perform the necessary action accordingly.
Table 9.  External Memory Interface Error Message Bits Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in generic_sdm_data_out signal)

32 31:24 Reserved
23:16 Address of sector with error
15:8 Reserved
7:4 Error Type:
  • 0000—SEU error
  • 0001—SDM and subsystem ECC Error
  • 0010—miscellaneous CNT error3
  • 0011—SmartVID error
  • 0100—miscellaneous SDM error
  • 0101—External Memory Interface
  • Remaining values—reserved
3:0 Reserved

Error data

(Least significant 32-bit word in generic_sdm_data_out signal)

32 31:25 Reserved
24:17 EMIF_ID
16:10 SOURCE_ID
9:6

External memory interface error type:

  • 4'd1—ECC_RMW_READ_LINK_DB
  • 4'd2—ECC_READ_LINK_DBE
  • 4'd3—ECC_READ_LINK_SBE
  • 4'd4—ECC_WRITE_LINK_DBE
  • 4'd5—ECC_WRITE_LINK_SBE
  • 4'd6—ECC_MULTI_DBE
  • 4'd7—ECC_SINGLE_DBE
  • 4'd8—ECC_MULTI_SBE
  • 4'd9—ECC_SINGLE_SBE
5:0 DDR_ADDR_MSB
Note: When an External Memory Interface error occurs, refer to the error data at bit [9:6] for the error type and perform the necessary action accordingly.
Important: For uncorrectable SDM ECC error, Altera recommends that you reconfigure the Agilex™ 5 device.
3 Contact Intel Premier Support and quote ID #15015577051 for further assistance when you see this error.
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