SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

ID 813649
Date 9/20/2024
Public

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2.4.1.2. On-Chip Lookup Sensitivity Processing

For the on-chip sensitivity processing, the Advanced SEU Detection Intel® FPGA IP reads the error message queue content and then compares single-bit error locations with a sensitivity map. This check determines whether or not the failure affects the device operation.
Figure 2. System Overview for On-Chip Lookup Sensitivity Processing with Advanced SEU Detection Intel® FPGA IP


Figure 3. Process Flow for On-Chip Lookup Sensitivity Processing