SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813649
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 5 SEU Mitigation Overview 2. Agilex™ 5 CRAM Error Mitigation 3. Retrieving SEU Statistic using Mailbox Command 4. Secure Device Manager ECC and SmartVID Errors Detection 5. Agilex™ 5 SEU Mitigation Implementation Guides 6. IP and Software References 7. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs
1. Agilex™ 5 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Agilex™ 5 CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.2. Error Message Queue x
2.2.1. SEU_ERROR Pin Behavior 2.2.2. Retrieving the Error Message Queue Contents Through Mailbox Command 2.2.3. Retrieving the Error Message Queue Content Using the HPS SDM Mailbox 2.2.4. Error Message Queue Bit Description
2.3. Scrubbing x
2.3.1. Internal Scrubbing 2.3.2. External Scrubbing
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
4. Secure Device Manager ECC and SmartVID Errors Detection x
4.1. SDM ECC Error Message Bits 4.2. SmartVID Error Message Bits 4.3. SDM ECC and SmartVID Errors Signals Behavior
5. Agilex™ 5 SEU Mitigation Implementation Guides x
5.1. Setting the SEU_ERROR Pin 5.2. Setting Up the SEU Mitigation Features 5.3. Performing External Scrubbing 5.4. Assigning Regions for Hierarchy Tagging 5.5. Sensitivity Map Header 5.6. Using the Fault Injection Debugger
5.5. Sensitivity Map Header x
5.5.1. Programming the .smh File into Memory 5.5.2. Looking up the Sensitivity Map Header
5.5.2. Looking up the Sensitivity Map Header x
5.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
5.6. Using the Fault Injection Debugger x
5.6.1. Launching and Setting Up the Fault Injection Debugger 5.6.2. Configuring Your Device using a Software Object File (.sof) 5.6.3. Constraining Regions for Fault Injection 5.6.4. Injecting Errors to Predefined Safe Locations 5.6.5. Blowing Fuse Bit to Enable Injecting All Error Types 5.6.6. Injecting Errors to Random Locations 5.6.7. Injecting Errors to Specific Locations 5.6.8. Injecting Double Adjacent Errors 5.6.9. Injecting SDM ECC Errors
5.6.4. Injecting Errors to Predefined Safe Locations x
5.6.4.1. Listing the Predefined Safe Locations: Command-Line Interface 5.6.4.2. Injecting Errors to Predefined Safe Locations: Command-Line Interface 5.6.4.3. Injecting Errors to Predefined Safe Locations: GUI with Tcl Console 5.6.4.4. Injecting Error to Predefined Safe Locations: Mailbox Command
5.6.8. Injecting Double Adjacent Errors x
5.6.8.1. Injecting Double Adjacent Errors: Command-Line Interface 5.6.8.2. Injecting Double Adjacent Errors: GUI with Tcl Console
5.6.9. Injecting SDM ECC Errors x
5.6.9.1. Injecting SDM ECC Errors: Command-Line Interface 5.6.9.2. Injecting SDM ECC Errors: GUI with Tcl Console 5.6.9.3. Injecting SDM ECC Errors: Fault Injection Debugger 5.6.9.4. Injecting SDM ECC Errors: Mailbox Command
6. IP and Software References x
6.1. Advanced SEU Detection Intel® FPGA IP References 6.2. Fault Injection Debugger Software References
6.1. Advanced SEU Detection Intel® FPGA IP References x
6.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 6.1.2. Advanced SEU Detection Intel® FPGA IP Ports
6.2. Fault Injection Debugger Software References x
6.2.1. Fault Injection Debugger GUI Tool 6.2.2. Fault Injection Debugger Command-Line Interface
1. Agilex™ 5 SEU Mitigation Overview
2. Agilex™ 5 CRAM Error Mitigation
3. Retrieving SEU Statistic using Mailbox Command
4. Secure Device Manager ECC and SmartVID Errors Detection
5. Agilex™ 5 SEU Mitigation Implementation Guides
6. IP and Software References
7. Document Revision History for the SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

1.1. SEU Mitigation Techniques

The Quartus® Prime software offers several features to detect, correct, and characterize the effects of SEU on your designs. Additionally, Agilex™ 5 FPGAs contain dedicated circuitry to help detect and correct errors.

Agilex™ 5 SEU mitigation features can benefit the system by:

  • Ensuring the system functions properly at all time
  • Preventing a system malfunction caused by an SEU event
  • Handling the SEU event if it is critical to the system
Table 1.  SEU Mitigation Areas and Approaches for Agilex™ 5 Devices
Area SEU Mitigation Approach
Error detection and correction Enable the error detection and correction (EDC) feature to detect Configuration Random Access Memory (CRAM) SEU events and automatically correct the CRAM contents.
Memory block error correction code Take advantage of the error correction code (ECC) feature and the special layout design of the Agilex™ 5 M20K memory blocks to reduce SEU failures in time (FIT) rate to almost zero.
SEU sensitivity processing Use the sensitivity processing feature to identify if the SEU on a CRAM bit location is critical to the function of your compiled FPGA design bitstream file.
Fault injection

Use the fault injection feature to help you validate system response to the SEU event by intentionally changing the CRAM state to trigger an error.

Agilex™ 5 supports ECC error injection to M20K blocks.

Hierarchy tagging Use hierarchy tagging, together with sensitivity processing and fault injection, to report SEU and constrain error injection to specific portions of your design logic.
Triple modular redundancy Use triple modular redundancy (TMR) technique on critical logic such as state machines to improve hardware fault tolerance.

For more information about ECC error injection to the M20K blocks, refer to the Agilex™ 5 Embedded Memory User Guide.

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