SEU Mitigation User Guide: Agilex™ 5 FPGAs and SoCs

ID 813649
Date 9/20/2024
Public

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Document Table of Contents

2.2.4. Error Message Queue Bit Description

Table 4.  SEU Error Message Queue Bit Description
Name Width Bit Description

Sector address

(Most significant 32-bit word in avst_seu_source_data signal)

32 31:24 Reserved
23:16 Sector address of the error
15:8 Reserved
7:4 Error type:
  • 0000—SEU error
  • 0001—SDM and subsystem ECC error
  • 0010—miscellaneous CNT error 1
  • 0011—SmartVID error
  • 0100—miscellaneous SDM error
  • Remaining values—reserved
3:0 Reserved

Error location 2

(Least significant 32-bit word in avst_seu_source_data signal)

32 31:29 Error type:
  • 001—single bit error
  • 010—double adjacent bit error
  • 011—uncorrectable multiple bits error
28 Correction status:
  • 0—not corrected
  • 1—corrected
27:25 Reserved
24:12 Bit position within the frame
11:0 Combination of row and frame index
1 Contact Intel Premier Support and quote ID #15015577051 for further assistance when you see this error.
2 For single bit error with internal scrubbing, the error location provides the error bit position. For multiple bit errors or single bit error without internal scrubbing, bit [24:0] returns 0.