AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

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ID 776775
Date 5/19/2023
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Document Table of Contents
Document Table of Contents x
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs x
AC Coupling and DC Coupling TDS I/O On-Chip Termination TDS I/O External Termination Termination and Biasing Schemes for TDS Transmitters and Receivers Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter Summary Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
AC Coupling and DC Coupling x
Capacitors and Components Selection
Termination and Biasing Schemes for TDS Transmitters and Receivers x
Schematic Topology for Transmitter and Receiver Buffers Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver x
Simulation Results
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter x
Simulation Results
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

Termination and Biasing Schemes for TDS Transmitters and Receivers

In this application note, the Intel Agilex® 7 M-Series FPGA interfaces with the Intel® Arria® 10 FPGA. The Intel® Arria® 10 FPGA represents a device that supports the listed JEDEC-compliant I/O standards.
Table 3.  Differential Signaling and I/O Standards— Intel® Arria® 10 Specifications
Voltages (V) I/O Standard
LVDS RSDS Mini-LVDS LVPECL
VCCIO Min. 1.71 1.71 1.71 1.71
Typ. 1.8 1.8 1.8 1.8
Max. 1.89 1.89 1.89 1.89
VID Min. 0.1 0.1 0.2 0.3
Cond. VCM = 1.25 V VCM = 1.25 V — —
Max. — — 0.6 —
VICM Min. 0 1 0.3 0.4 0.6 1
Cond.

Data rate ≤ 700 Mbps

Data rate > 700 Mbps

 — —

Data rate ≤ 700 Mbps

Data rate > 700 Mbps
Max. 1.85 1.6 1.4 1.325 1.7 1.6
VOD Min. 0.247 0.1 0.25 —
Typ. — 0.2 — —
Max. 0.6 0.6 0.6 —
VOCM Min. 1.125 0.5 1 —
Typ. 1.25 1.2 1.2 —
Max. 1.375 1.4 1.4 —

Section Content
Schematic Topology for Transmitter and Receiver Buffers
Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL

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