AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

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ID 776775
Date 5/19/2023
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Document Table of Contents
Document Table of Contents x
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs x
AC Coupling and DC Coupling TDS I/O On-Chip Termination TDS I/O External Termination Termination and Biasing Schemes for TDS Transmitters and Receivers Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter Summary Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
AC Coupling and DC Coupling x
Capacitors and Components Selection
Termination and Biasing Schemes for TDS Transmitters and Receivers x
Schematic Topology for Transmitter and Receiver Buffers Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver x
Simulation Results
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter x
Simulation Results
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver

In the receiver simulations, the JEDEC-compliant LVDS transmitter is the Intel® Arria® 10 FPGA. The TDS receiver is the Intel Agilex® 7 M-Series FPGA.
Table 4.  Simulation Conditions
Item Conditions
Simulator Siemens* HyperLynx LineSim VX.2.11_Update2 build 20026110
Transmitter Intel® Arria® 10 FPGA LVDS buffer
Receiver Intel Agilex® 7 M-Series FPGA 1.05 V, 1.1 V, 1.2 V, and 1.3 V TDS buffers
Data Rate 600 Mbps
Encoding 8b/10b with 10-bit order
Measurement At the far end receiver
Figure 4. Simulation Topology



Section Content
Simulation Results

Level Two Title