AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

ID 776775
Date 5/19/2023
Public

Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter

In the transmitter simulation, the TDS transmitter is the Intel Agilex® 7 M-Series FPGA. The JEDEC-compliant LVDS receiver is the Intel® Arria® 10 FPGA.
Table 5.  Simulation Conditions
Item Conditions
Simulator Siemens* HyperLynx LineSim VX.2.11_Update2 build 20026110
Transmitter Intel Agilex® 7 M-Series FPGA 1.3 V TDS buffer
Receiver Intel® Arria® 10 FPGA LVDS buffer
Data Rate 600 Mbps and 750 Mbps
Measurement At the far end receiver
Figure 9. Simulation Topology—Data Rate ≤ 700 Mbps (600 Mbps)


Figure 10. Simulation Topology—Data Rate > 700 Mbps (750 Mbps)