AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

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ID 776775
Date 5/19/2023
Public
Document Table of Contents
Document Table of Contents x
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs x
AC Coupling and DC Coupling TDS I/O On-Chip Termination TDS I/O External Termination Termination and Biasing Schemes for TDS Transmitters and Receivers Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter Summary Document Revision History for AN 555: True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs
AC Coupling and DC Coupling x
Capacitors and Components Selection
Termination and Biasing Schemes for TDS Transmitters and Receivers x
Schematic Topology for Transmitter and Receiver Buffers Recommended Topologies for TDS, LVDS, RSDS, Mini-LVDS, and LVPECL
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Receiver x
Simulation Results
Simulation: Intel Agilex® 7 M-Series FPGA as TDS Transmitter x
Simulation Results
True Differential Signaling Termination and Biasing for Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs

TDS I/O On-Chip Termination

All I/O and dedicated clock input pins in Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs support on-chip differential termination (RD OCT). The FPGAs provide a 100Ω RD OCT option on each differential receiver channel for the TDS I/O standard.
Note: For interfaces that require external voltage bias circuitry near the true differential receivers of the Intel Agilex® 7 M-Series and Intel Agilex® 5 FPGAs, disable the RD OCT resistor.
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